Clock management for power reduction in a video display sub-system

• US 5,615,376 A
• Filed: 08/03/1994
• Issued: 03/25/1997
• Est. Priority Date: 08/03/1994
• Status: Expired due to Term

• Current Assignee: Faust Communications LLC (Intellectual Ventures LLC)
• Original Assignee: Neomagic Corporation
• Inventors: Ranganathan, Ravi
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US08/285,401
• Time in Patent Office: 965 Days
• Field of Search: 395/162, 395/163, 395/164, 395/750, 395/117, 395/129, 395/133, 395/550, 395/800
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3218 of display devices
• CPC Class Codes: G06F 1/3265 Power saving in display device
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 5/18 Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A video sub-system features reduced power consumption by periodically disabling the video controller clocks used for transferring pixel data to a screen. The video clocks are pulsed only when pixel data is being transferred to the screen, during the time that a horizontal line of pixels is being scanned on the screen. The video clocks are not pulsed during the horizontal and vertical blanking periods, when the electron beam in a cathode-ray-tube is being re-traced. The video clocks are also not pulsed during a recovery period for a flat-panel screen. A video memory contains pixel information for the entire screen and is controlled by a memory controller. The memory controller uses a memory clock to transfer all or part of a horizontal line of pixels to a video buffer. The pixel data is then read out of the video buffer to the screen in a serial fashion, synchronized to the video clock. Host data may be written to a host buffer using a bus clock from the host, and then written to the video memory using the memory clock. The memory clock is only pulsed when data is transferred to or from the video memory, or during memory refresh. The memory clock is not pulsed when the video memory is idle. Power consumption is reduced by enabling or pulsing the memory clock and the internal bus clock only when a transfer request is received, pending, or in progress.

Claims

1. A video sub-system for displaying an image on a screen, the video sub-system comprising:

clock generation means for generating a video clock, the video clock for transferring pixels of display information for display by the screen during a scanning period of time, the video clock pulsing during the scanning period of time;

blanking means, coupled to the clock generation means, for periodically disabling the video clock during a blanking period of time, the video clock not pulsing during the blanking period of time;

video memory means for storing pixels of display information for a whole screen;

memory controller means, responsive to a memory clock, for controlling transfer of the pixels of display information to and from the video memory means;

video buffer means, receiving the pixels of display information from the memory controller means, for storing a subset of the pixels of display information from the video memory means;

serial transfer means, coupled to receive the subset of the pixels of display information from the video buffer means, for transferring pixels of display information to the screen, the pixels of display information being transferred to the screen serially in synchronization to the video clock, the video clock pulsing at least once for every pixel being transferred to the screen, each pixel representing a point on the screen;

second clock generation means for generating the memory clock, the second clock generation means including

means for receiving a periodic request for a memory transfer from the video buffer means;

means for enabling and pulsing the memory clock in response to the periodic request; and

means for disabling the memory clock and not pulsing the memory clock once the subset of the pixels of display information from the video memory means is loaded into the video buffer means;

a host buffer, including

means for receiving display update information from a host;

means for generating a host request to the second clock generation means;

means for enabling and pulsing the memory clock in response to the host request; and

means for disabling the memory clock and not pulsing the memory clock once the display update information from the host is written to the video memory means,

whereby the memory clock is not pulsed after a memory transfer or a host transfer is completed, reducing power consumption by the video sub-system, and

whereby the image is displayed on the screen using the video clock that is periodically disabled, reducing power consumption during display of the image.

2. The video sub-system of claim 1 wherein the serial transfer means further comprises:

conversion means, for converting the subset of the pixels of display information from the video buffer means into pixels of display information in a display format for display on the screen,

whereby the pixels of display information from the video memory means are converted by the conversion means into pixels that are in a display format for display on the screen.

3. The video sub-system of claim 1 wherein the blanking period of time is a horizontal blanking period.

4. The video sub-system of claim 1 wherein the blanking period of time is a vertical blanking period.

5. The video sub-system of claim 2 wherein the conversion means comprises:

an attribute controller, receiving the subset of the pixels of display information from the video buffer means, for modifying attributes of the pixels of display information;

a RAM digital-to-analog converter, coupled to the attribute controller, for re-mapping a color represented by a pixel and converting the pixel to an analog signal for transmission to the screen.

6. The video sub-system of claim 5 wherein the conversion means further comprises:

a flat-panel controller, coupled to the RAM digital-to-analog converter and receiving a re-mapped pixel from the RAM digital-to-analog converter, for converting the color represented by the pixel into a shade of gray for display on a flat-panel display screen.

7. A clock generation circuit for a video sub-system, the clock generation circuit comprising:

a clock input, the clock input being coupled to receive a free-running clock;

a first clock synthesizer, receiving the free-running clock from the clock input, the first clock synthesizer pulsing a memory source clock when a first standby mode is inactive, the first clock synthesizer not pulsing a memory source clock when the first standby mode is active, the memory source clock having a first frequency, the first frequency for accessing a video memory;

multiplexer means, receiving the free-running clock from the clock input and receiving the memory source clock from the first clock synthesizer, for selecting the free-running clock when the first standby mode is active, the multiplexer means selecting the memory source clock when a first standby mode is inactive, the multiplexer means outputting a first source clock;

a first clock gating circuit, receiving the first source clock from the multiplexer means, and receiving a transfer request, the first clock gating circuit outputting the first source clock when the transfer request is received, the first clock gating circuit outputting a constant signal if the transfer request is not received, the first clock gating circuit outputting the constant signal upon completion of a transfer, the constant signal being absent any clock pulses;

a video clock synthesizer, receiving the free-running clock from the clock input, the video clock synthesizer pulsing a video source clock when a video standby mode is inactive, the video clock synthesizer not pulsing a video source clock when the video standby mode is active, the video source clock having a video frequency, the video frequency for providing pixels to a display screen; and

a video clock gating circuit, receiving the video source clock from the video clock synthesizer, and receiving a periodic request, the video clock gating circuit outputting the video source clock when the periodic request is received, the video clock gating circuit outputting a constant signal if the periodic request is not received, the video clock gating circuit outputting the constant signal upon completion of a periodic transfer, the constant signal being absent any clock pulses,

whereby power consumption is reduced by outputting the first source clock when a transfer is pending but otherwise outputting the constant signal and by outputting the video source clock when a periodic transfer is pending but otherwise outputting the constant signal.

8. The clock generation circuit of claim 7 further comprising

a second clock gating circuit, receiving the first source clock from the multiplexer means, and receiving a block transfer request, the second clock gating circuit outputting the first source clock when the block transfer request is received, the second clock gating circuit outputting a constant signal if the block transfer request is not received, the second clock gating circuit outputting the constant signal upon completion of a block transfer, the constant signal being absent any clock pulses, the second clock gating circuit outputting the first source clock to a block transfer engine,

whereby power consumption is reduced by outputting the first source clock to the block transfer engine when a block transfer is pending but otherwise outputting the constant signal to the block transfer engine.

9. The clock generation circuit of claim 7 further comprising programmable means for setting the video frequency, coupled to the video clock synthesizer, for setting the video frequency in response to a video resolution mode to be displayed,

whereby the video frequency is adjusted for different video resolutions.

10. The clock generation circuit of claim 9 further comprising

a flat-panel clock gating circuit, receiving the video source clock from the video clock synthesizer, and receiving the periodic request, the flat-panel clock gating circuit outputting a flat-panel clock derived from the video source clock when the periodic request is received and a flat-panel display mode is enabled, the flat-panel clock gating circuit outputting a constant signal if the periodic request is not received, or upon completion of a periodic transfer, or the flat-panel display mode is disabled, the constant signal being absent any clock pulses.

11. A video memory controller comprising:

memory clock generation means for generating a memory clock, the memory clock for synchronizing access of display information for display by a screen;

the memory clock generation means including;

means for receiving a request for a memory transfer from a requestor;

means for enabling and pulsing the memory clock in response to the request;

means for disabling the memory clock and not pulsing the memory clock once the memory transfer is complete,

video memory means for storing display information for the screen; and

memory controller means, responsive to the memory clock, for controlling the memory transfer, the memory controller means transferring the display information to and from the video memory means using the memory clock;

a host buffer, receiving display update information from a host; and

host means, responsive to the host buffer, for generating the request for a memory transfer when the host buffer receives display update information from the host,

the memory clock generation means enabling and pulsing the memory clock in response to the request, the memory clock generation means disabling the memory clock and not pulsing the memory clock once the display update information from the host is written to the video memory means,

whereby the video memory controller uses the memory clock that is disabled when no transfer is occurring, and the memory clock is not pulsed after a host transfer is completed, reducing power consumption.

12. The video memory controller of claim 11 further comprising:

video buffer means, receiving the display information from the memory controller means, for storing a subset of the display information from the video memory means; and

video buffer request means, responsive to the video buffer means, for generating the request for a memory transfer when the video buffer means requires replenishing of the subset of the display information;

whereby the memory clock is generated in response to the request for a memory transfer when the video buffer means requires replenishing, reducing power consumption by the video sub-system.

13. A video memory controller comprising:

memory clock generation means for generating a memory clock, the memory clock for synchronizing access of display information for display by a screen;

the memory clock generation means including;

means for receiving a request for a memory transfer from a requestor;

means for enabling and pulsing the memory clock in response to the request;

means for disabling the memory clock and not pulsing the memory clock once the memory transfer is complete,

video memory means for storing display information for the screen; and

memory controller means, responsive to the memory clock, for controlling the memory transfer, the memory controller means transferring the display information to and from the video memory means using the memory clock;

wherein the means for receiving the request for the memory transfer from the requestor includes

means for receiving synchronous requests; and

means for receiving asynchronous requests;

synchronizing means, coupled to the means for receiving synchronous requests, for synchronizing the asynchronous requests and inputting the asynchronous requests after synchronization to the means for receiving synchronous requests when the memory clock is disabled, the synchronizing means inputting the asynchronous requests before synchronization when the memory clock is enabled,

whereby the video memory controller uses the memory clock that is disabled when no transfer is occurring, reducing power consumption and whereby a synchronization delay is avoided when the memory clock is already enabled.

14. The video memory controller of claim 13 wherein the synchronous requests include:

a transfer in progress indication from the memory controller means, indicating that the memory transfer is not yet complete;

a BLT request from a BLT engine; and

a hardware cursor request from a hardware cursor display means;

and wherein the asynchronous requests include;

a video buffer request indicating a need to refresh a video buffer for transferring the display information to the screen; and

a host request indicating a request for data transfer to the video memory means from a host.