System having independently addressable bus interfaces coupled to serially connected multi-ported signal distributors generating and maintaining frame based polling schedule favoring isochronous peripherals

• US 5,615,404 A
• Filed: 10/31/1994
• Issued: 03/25/1997
• Est. Priority Date: 10/31/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bhatt, Ajay V., Volk, Andrew M., Callahan, Shelagh, Morriss, Jeff C., Nizar, Puthiya K., Haslam, Richard M., Knoll, Shaun, Cadambi, Sudarshan B.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Nahm, Sang Y.
• Application Number:
  US08/332,255
• Time in Patent Office: 876 Days
• Field of Search: 395/822, 395/837, 395/838, 395/848, 395/857, 395/866, 395/882, 395/864, 395/823, 395/290, 395/421.01, 370/13, 370/85.8, 370/85.6, 370/94.1
• US Class Current: 710/62
• CPC Class Codes: G06F 13/423 with synchronous protocol
• CPC Class Codes: H04L 12/40058 Isochronous transmission
• CPC Class Codes: H04L 12/40078 Bus configuration home automation networks H04L12/2803; arrangements for maintenance or administration H04L41/00

Abstract

A bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces are provided for form an hierarchical serial bus assembly for serially interfacing a number of isochronous and asynchronous peripherals to the system unit of a computer system. The bus controller, bus signal distributors, and bus interfaces are provided with circuitry and complementary logic for implementing a master/slave model of flow control for serially interfacing the bus agents to each other to conduct data communication transactions. In certain embodiments, these circuitry and complementary logic further conduct connection management transactions employing also the master/slave model of flow control, implement a frame based polling schedule for polling the slave "devices", employ at least two address spaces to conduct the various transactions, support communication packet based transactions, and/or electrically represent data and/or control states.

Claims

1. A serial bus assembly for serially interfacing one or more isochronous and/or asynchronous peripherals to a system unit of a computer system, the serial bus assembly comprising:

one or more independently addressable bus interfaces, one for each peripheral, for independently coupling the peripherals to the system unit, conducting bus management transactions including configuration management transactions with a bus master, and facilitating data transactions with independently addressable functions of their respective peripherals, each peripheral having one or more independently addressable functions, responsive to authorizations received from the bus master, each bus interface being a terminal point of the serial bus assembly;

zero or more independently addressable bus signal distributors, each having a plurality of ports, for coupling said one or more bus interfaces upstream towards the bus master, and serving as conduits for bus signal distributions, wherein if the serial bus assembly has only a single bus interface, the single bus interface is coupled to the bus master, and if the serial bus assembly has more than one bus interface, each bus interface is coupled upstream to a bus signal distributor, and each bus signal distributor is in turn coupled upstream to another bus distributor, except for one bus signal distributor, which is coupled upstream to the bus master;

an addressable bus controller coupled upstream to the system unit, and downstream to either a bus signal distributor or a bus interface depending on the number of bus interfaces included in the serial bus assembly, for functioning as the bus master, authorizing the zero or more bus signal distributors, the bus interface(s) and the function(s) of the peripheral(s) to conduct transactions, conducting management transactions including configuration management transactions with the zero or more bus signal distributors and the bus interface(s), and facilitating data transactions with the system unit, said bus controller dynamically generating and maintaining a frame based polling schedule for polling said functions of said peripherals for data communication transactions, said dynamically generated and maintained frame based polling schedule favoring isochronous peripherals over asynchronous peripherals.

2. The apparatus as set forth in claim 1, wherein said bus controller dynamically determines and keeps track of connection topology between said bus controller, said zero or more bus signal distributors, and said one or more bus interfaces.

3. The apparatus as set forth in claim 1, wherein said bus controller, said bus signal distributors and said bus interfaces support a geographical and a logical address space, said bus controller polls said functions of said peripherals for data transactions in said logical address space.

4. The apparatus as set forth in claim 1, wherein said bus controller further polls said zero or more bus signal distributors and said one or more bus interfaces for management transactions including configuration management transactions in said dynamically generated and maintained frame based polling schedule.

5. The apparatus as set forth in claim 1, wherein said bus controller, said bus signal distributors and said bus interfaces support a geographical and a logical address space, said bus controller polls said bus signal distributors and said one or more bus interfaces for management transactions including configuration management transactions in said geographical address space.

6. The apparatus as set forth in claim 1, wherein said bus controller employs a number of element packets having packet types identified by packet identifiers to create communication packets for facilitating data transactions with said system unit and/or said functions of said peripherals, and for conducting management transactions including configuration management transactions with said zero or more bus signal distributors and said one or more bus interfaces, said bus controller, said zero or more bus signal distributors, and said one or more bus interfaces employing a predetermined control flow protocol for exchanging said communication packets.