Fully planarized thin film transistor (TFT) and process to fabricate same

• US 5,616,934 A
• Filed: 03/22/1996
• Issued: 04/01/1997
• Est. Priority Date: 05/12/1993
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Dennison, Charles H., Manning, Monte
• Primary Examiner(s): Crane, Sara W.
• Assistant Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US08/621,766
• Time in Patent Office: 375 Days
• Field of Search: 257/66-70, 257/296, 257/347, 257/412, 257/634, 257/774, 257/330, 257/332, 257/333, 257/377, 257/903, 437/193, 437/240
• US Class Current: 257/67
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell
• CPC Class Codes: Y10S 438/964 Roughened surface

Abstract

The invention is directed to a thin film transistor (TFT) fabricated by using a planarized poly plug as the bottom gate for use in any integrated circuit and in particular an static random access memory (SRAM). The TFT is used in an SRAM device to form a planarized SRAM cell comprising: a pulldown transistor having a control gate and source/drain terminals; a planarized insulating layer having grooves therein, each groove providing access to an underlying conductive material; a planarized conductive plug residing inside each groove, whereby a first conductive plug forms a thin film transistor gate connecting to an to an adjacent inverter and a second conductive plug provides connection to the gate of the pulldown device; a gate dielectric overlying the first planarized conductive plug; and a patterned semiconductive layer doped such that a channel region aligns to each thin film transistor gate and a source/drain region aligns to each side of the channel region is formed.

Claims

1. A transistor fabricated on a substrate assembly having a conductive region formed therein, comprising:

a generally insulating material having an opening therein defined in part by a sidewall, said opening extending from a top surface to said conductive region in said substrate assembly;

a conductive silicon material within said opening, said conductive silicon material in physical contact with said sidewall of said insulating material and in electrical contact with said conductive region;

a gate dielectric overlying said conductive silicon material; and

at least two semiconductor regions defining source and drain areas overlying said gate dielectric, said source and drain areas in operative relation to said conductive silicon material to form said transistor.

2. The transistor of claim 1, wherein said conductive silicon material comprises conductively doped polysilicon.

3. The transistor of claim 1, wherein said opening in said generally insulating material comprises a groove formed therein.

4. The transistor of claim 1, wherein said source and drain areas are defined in a polysilicon layer deposited over said gate dielectric.

5. The transistor of claim 1, wherein said conductive region is formed in a semiconductor substrate.

6. The transistor of claim 5, wherein said conductive region comprises a doped region in said substrate.

7. A transistor fabricated on a substrate assembly having a conductive region formed therein, comprising:

a generally insulating material having an opening therein defined in part by a sidewall, said opening extending from a top surface to said conductive region in said substrate assembly;

a conductive silicon material within said opening, said conductive silicon material in physical contact with said sidewall of said insulating material and in electrical contact with said conductive region;

a gate dielectric overlying said conductive silicon material;

at least two semiconductor regions defining source and drain areas overlying said gate dielectric, said source and drain areas in operative relation to said conductive silicon material to form said transistor; and

a conductive layer formed on said substrate, said conductive layer extending into electrical contact with said conductive silicon material within said opening.

8. The transistor of claim 7, wherein said conductive silicon material comprises conductively doped polysilicon.

9. The transistor of claim 7, wherein said opening in said generally insulating material comprises a groove formed therein.

10. The transistor of claim 7, wherein said source and drain areas are defined in a polysilicon layer deposited over said gate dielectric.

11. The transistor of claim 7, wherein said conductive region is formed in a semiconductor substrate.

12. The transistor of claim 11, wherein said conductive region comprises a doped region in said substrate.

13. A thin film transistor (TFT) fabricated on a starting substrate, said TFT comprising:

a planarized insulating layer overlying said starting substrate;

at least a single groove with continuous sidewalls having no intermediate horizontal insulating surfaces, said sidewalls extending from the surface of said planarized insulating layer to at least one underlying electrically conductive material;

a conductively doped semiconductive material residing inside said groove, the material'"'"'s surface being on essentially the same level as said planarized insulating layer'"'"'s surface, said semiconductive material'"'"'s surface forming said TFT gate;

a TFT gate dielectric overlying said TFT gate; and

a semiconductive layer overlying said gate dielectric, said semiconductive layer consisting of a channel region above said TFT gate and source/drain regions to each side of said channel region.

14. The thin film transistor of claim 13, wherein said conductively doped semiconductive material comprises conductively doped polysilicon.

15. The thin film transistor of claim 13, wherein said semiconductive layer comprises conductively doped polysilicon.

16. The thin film transistor of claim 13, wherein said planarized insulating layer comprises a planarized BPSG layer and an overlying nitride layer.

17. The thin film transistor of claim 13, wherein said planarized insulating layer comprises a planarized BPSG layer and an overlying undoped oxide layer.

18. A thin film transistor fabricated on a starting substrate, said thin film transistor comprising:

a planarized insulating layer overlying said starting substrate;

at least a single groove with continuous vertical sidewalls having no intermediate horizontal insulating surfaces, said sidewalls extending from the surface of said planarized insulating layer to at least one underlying electrically conductive material;

a conductively doped semiconductive material residing inside said groove, the material'"'"'s upper surface being on essentially the same level as said planarized insulating layer'"'"'s surface, said semiconductive material'"'"'s upper surface forming said TFT gate and the semiconductive material'"'"'s lower surface making contact to a diffusion region and a conductive interconnect;

a TFT gate dielectric overlying said TFT gate;

a semiconductive layer overlying said gate dielectric, said semiconductive layer consisting of a channel region above said TFT gate and source/drain regions to each side of said channel region.

19. The thin film transistor of claim 18, wherein said conductively doped semiconductive material comprises conductively doped polysilicon.

20. The thin film transistor of claim 18, wherein said semiconductive layer comprises conductively doped polysilicon.

21. The thin film transistor of claim 18, wherein said planarized insulating layer comprises a planarized BPSG layer and an overlying nitride layer.

22. The thin film transistor of claim 18, wherein said planarized insulating layer comprises a planarized BPSG layer and an overlying undoped oxide layer.

23. A thin film transistor fabricated on a starting substrate, said thin film transistor comprising:

a planarized insulating layer overlying said starting substrate, said planarized insulating layer having first and second grooves therein;

at least a single groove with continuous essentially vertical sidewalls and having no intermediate horizontal insulating surfaces, said sidewalls extending from the surface of said planarized insulating layer to at least one underlying electrically conductive terminal;

a conductively doped semiconductive material residing inside said groove, the material'"'"'s upper surface being on essentially the same level as said planarized insulating layer'"'"'s surface, said semiconductive material'"'"'s upper surface forming said TFT gate and the semiconductive material'"'"'s lower surface making contact to a diffusion region and a conductive interconnect;

a TFT gate dielectric overlying said TFT gate;

a semiconductive layer overlying said gate dielectric, said semiconductive layer consisting of a channel region above said TFT gate and source/drain regions to each side of said channel region;

one of said source/drain terminals extending to and filling said second groove, thereby making contact to a second underlying conductive terminal.

24. The thin film transistor of claim 23, wherein said conductively doped semiconductive material comprises conductively doped polysilicon.

25. The thin film transistor of claim 23, wherein said semiconductive layer comprises conductively doped polysilicon.

26. The thin film transistor of claim 23, wherein said planarized insulating layer comprises a planarized BPSG layer and an overlying nitride layer.

27. The thin film transistor of claim 23, wherein said planarized insulating layer comprises a planarized BPSG layer and an overlying undoped oxide layer.

28. The thin film transistor of claim 23, wherein said one of said source/drain terminals conformally fills said second groove.

29. A thin film transistor (TFT) fabricated on a starting substrate, said thin film transistor comprising:

a planarized insulating layer overlying said starting substrate, said planarized insulating layer having first and second grooves therein;

said first and second grooves having continuous essentially vertical sidewalls and having no intermediate horizontal insulating surfaces, said sidewalls extending from the surface of said planarized insulating layer to at least one underlying electrically conductive terminal;

a conductively doped semiconductive material residing inside said first and second grooves, the material'"'"'s upper surface being on essentially the same level as said planarized insulating layer'"'"'s surface, the semiconductive material'"'"'s upper surface residing in said first groove forming said TFT gate with the semiconductive material'"'"'s lower surface making contact to said underlying electrically conductive terminal;

a TFT gate dielectric overlying said TFT gate;

a semiconductive layer overlying said gate dielectric, said semiconductive layer consisting of a channel region above said TFT gate and source/drain regions to each side of said channel region;

one of said source/drain terminals electrically coupling to said semiconductive material residing in said second groove.

30. The thin film transistor of claim 29, wherein said conductively doped semiconductive material comprises conductively doped polysilicon.

31. The thin film transistor of claim 29, wherein said semiconductive layer comprises conductively doped polysilicon.

32. The thin film transistor of claim 29, wherein said planarized insulating layer comprises a layer of planarized oxide.

33. The thin film transistor of claim 29, wherein said planarized insulating layer comprises a BPSG layer overlaid with a nitride layer.

34. The thin film transistor of claim 29, wherein said planarized insulating layer comprises a planarized BPSG layer and an overlying undoped oxide layer.

35. The thin film transistor of claim 29, wherein said underlying electrically conductive terminal comprises at least one material selected from the group consisting of a conductively doped polysilicon and a conductively doped diffusion area.

36. An inverter fabricated on a starting substrate, said inverter comprising:

a pulldown transistor, said pulldown transistor having a control gate and source/drain terminals;

a planarized insulating layer over said pulldown transistor;

a first planarized conductive polysilicon plug forming a thin film transistor gate connecting to a coupling node and a second planarized conductive polysilicon plug providing connection to said control gate of said pulldown transistor;

a gate dielectric overlying said first planarized conductive polysilicon plugs;

a patterned polysilicon layer doped such that a channel region aligns to said thin film transistor gate and a source/drain region aligns to each side of said channel region.

37. The inverter of claim 36, wherein the connection between said first planarized conductive polysilicon plug and said coupling node and the connection between said second planarized conductive polysilicon plug and said control gate of said pulldown transistor are formed in a both a substantially vertical and substantially horizontal fashion.

38. The inverter of claim 36, wherein the connection between said first planarized conductive polysilicon plug and said coupling and the connection between said second planarized conductive polysilicon plug and said control gate of said pulldown transistor are formed in a only a substantially horizontal fashion.

39. A planarized cross-coupled latch fabricated on a starting substrate, comprising a first planarized inverter of claim 36 cross-coupled to a second planarized inverter of claim 36.

40. The planarized cross-coupled latch of claim 39, wherein said cross-coupled latch functions as a cross-coupled static storage cell in a static random access memory.