Flash EEPROM cell and manufacturing methods thereof
First Claim
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1. A flash EEPROM cell, comprising:
- a first source and a first drain formed in a p-type silicon substrate;
a second source and a second drain formed in an n-well of said p-type silicon substrate, with said second source connecting to said first drain;
a first tunnel oxide and a second tunnel oxide formed on said p-type silicon substrate between said first source and said first drain, and said p-type silicon substrate between said second source and said second drain respectively;
a first floating gate and a second floating gate formed on said first and second tunnel oxides, respectively, wherein said first floating gate is connected to said second floating gate;
a first insulating film and a second insulating film formed on said first and second floating gates, respectively; and
a first control gate and a second control gate formed on said first and second insulating films, respectively, with said first control gate connecting to said second control gate.
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Abstract
This invention relates to a flash EEPROM(Electrically Erasable Programmable Read-Only Memory) cell, more particularly to the cell having an inverter structure with an n-channel part and a p-channel part which hold a floating gate in common, in which the floating gate is charged with hot electrons produced in the n-channel part in programming and the floating gate is neutralized or inverted with hot holes produced in the p-channel part in erasing.
52 Citations
1 Claim
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1. A flash EEPROM cell, comprising:
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a first source and a first drain formed in a p-type silicon substrate; a second source and a second drain formed in an n-well of said p-type silicon substrate, with said second source connecting to said first drain; a first tunnel oxide and a second tunnel oxide formed on said p-type silicon substrate between said first source and said first drain, and said p-type silicon substrate between said second source and said second drain respectively; a first floating gate and a second floating gate formed on said first and second tunnel oxides, respectively, wherein said first floating gate is connected to said second floating gate; a first insulating film and a second insulating film formed on said first and second floating gates, respectively; and a first control gate and a second control gate formed on said first and second insulating films, respectively, with said first control gate connecting to said second control gate.
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Specification
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Current AssigneeHyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
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Original AssigneeHyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
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InventorsSong, Bok N.
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Primary Examiner(s)Ngo, Ngan V.
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Application NumberUS08/622,757Time in Patent Office370 DaysField of Search257/316, 257/317, 257/319, 257/321, 257/322US Class Current257/316CPC Class CodesH10B 69/00 Erasable-and-programmable R...
