Electrostatic discharge protection system for mixed voltage application specific integrated circuit design

• US 5,616,943 A
• Filed: 06/13/1994
• Issued: 04/01/1997
• Est. Priority Date: 09/29/1993
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: AT&T Global Network Services LLC (AT&T, Inc.), Symbios Logic Incorporated (Broadcom, Inc.), Hyundai Electronics America Incorporated (SK Hynix Inc.)
• Inventors: Nguyen, Hoang P., Walker, John D.
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US08/259,240
• Time in Patent Office: 1,023 Days
• Field of Search: 257/355, 257/356, 257/357, 257/360, 257/361, 257/362, 257/363, 257/203
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements

Abstract

An ESD protection system that makes use of several different types of over-voltage protection devices provides ESD conduction paths between different power lines. For example, the system may employ shunt diodes between the ground lines of the different power supplies and between I/O pads and power supply lines; SCR protection between I/O pads and ground; and thick field device protection between different power supply V_DD lines. In this way, a conduction path for an ESD event between two input, output power and ground pads may be implemented using the device whose switching characteristics are best suited to that application.

Claims

1. An integrated circuit having over-voltage protection, said circuit comprising:

a plurality of power input terminal sets, at least two of said plurality of power input terminal sets operable by a different one of a plurality of power voltages, each of said plurality of power input terminal sets including a ground terminal and a V_DD terminal operated at a potential more positive than its respective ground terminal; and

a plurality of active, over-voltage protection devices electrically connected to provide electrostatic discharge conduction paths among pairs of V_DD terminals and ground terminals,

wherein a first subgroup of said plurality of over-voltage protection devices provide multiple electrostatic discharge conduction paths between a V_DD terminal and a ground terminal of a first one of said plurality of power input terminal sets.

2. An integrated circuit as in claim 1, wherein at least one of said over-voltage protection devices is connected directly to said V_DD terminal and said ground terminal of said first one of said plurality of power input terminal sets.

3. An integrated circuit as in claim 1, wherein at least one of said over-voltage protection devices is a thick field device.

4. An integrated circuit as in claim 1, wherein at least one over-voltage protection device is electrically connected to said V_DD terminal of the first one of said plurality of power input terminal sets and a V_DD terminal of a second one of said plurality of power input terminal sets operated at different voltages.

5. An integrated circuit as in claim 4, wherein said at least one of said over-voltage protection devices is a thick field device having a first terminal connected to the V_DD terminal of the first one of said plurality of power input terminals sets and a second terminal connected to the V_DD terminal of the second one of said plurality of power input terminal sets.

6. An integrated circuit as in claim 4, wherein said V_DD terminal of the first one of said plurality of power input terminal sets applies a first potential, and said V_DD terminal of the second one of said plurality of power input terminal sets applies a second potential greater than said first potential.

7. An integrated circuit as in claim 1, wherein one of said plurality of over-voltage protection devices comprises first and second groups of series-connected diodes, electrically connected between the ground terminal of the first one of said plurality of power input terminal sets and a ground terminal of a second one of said plurality of power input terminal sets.

8. An integrated circuit as in claim 1, further comprising:

an input-output signal terminal; and

wherein a second subgroup of said plurality of over-voltage protection devices are electrically connected between said input-output signal terminal and terminals of a second one of said plurality of power input terminal sets.

9. An integrated circuit as in claim 8, wherein at least one of said plurality of over-voltage protection devices of said second subgroup is electrically connected between said input-output signal terminal and a V_DD terminal of said second one of said plurality of power input terminal sets.

10. An integrated circuit as in claim 9, wherein said at least one of said plurality of said over-voltage protection devices of said second subgroup is a diode.

11. An integrated circuit as in claim 10, wherein said diode is a parasitic diode including a MOS transistor having its gate electrically connected to its source and to said V_DD terminal of said second one of said plurality of power input terminal sets.

12. An integrated circuit as in claim 11, wherein said input-output terminal is an output terminal.

13. An integrated circuit as in claim 12, wherein said at least one of said plurality of over-voltage protection devices of said second subgroup further includes a MOS transistor output driver, and said parasitic diode is cooperatively established by said MOS transistor, having its gate electrically connected to its source, and by said output driver.

14. An integrated circuit as in claim 8, wherein at least one of said plurality of said over-voltage protection devices of said second subgroup is electrically connected between said input-output signal terminal and a ground terminal of said second one of said plurality of power input terminal sets.

15. An integrated circuit as in claim 14, wherein said at least one of said plurality of over-voltage protection devices of said second subgroup includes a diode.

16. An integrated circuit as in claim 15, wherein said diode is a parasitic diode including a MOS transistor having its gate electrically connected to its source and to said ground terminal of the second one of said plurality of power input terminal sets.

17. An integrated circuit as in claim 16, wherein said MOS transistor is an N-channel MOS transistor.

18. An integrated circuit as in claim 17, wherein said input-output terminal is an output terminal.

19. An integrated circuit as in claim 18, wherein said at least one of said plurality of over-voltage protection devices of said second subgroup further includes a MOS transistor output driver, and said parasitic diode is cooperatively established by said MOS transistor, having its gate electrically connected to its source, and by said output driver.

20. An integrated circuit as in claim 17, further comprising a resistor connected between said input-output terminal and said at least one of said plurality of over-voltage protection devices of said second subgroup.

21. An integrated circuit as in claim 15, wherein said plurality of over-voltage protection devices of said second subgroup include a silicon controlled rectifier in parallel with said diode.

22. A method for protecting an integrated circuit from over-voltages comprising the steps of:

receiving an over-voltage pulse at a first power input terminal;

establishing a first current path to conduct a portion of said pulse to a second power input terminal;

establishing a second current path from said first power input terminal to conduct a remainder of said pulse to a third power input terminal; and

establishing a current path from said second power input terminal to conduct said portion of said pulse to said third power input terminal.

23. A method as in claim 22, wherein at least one of said current-path-establishing steps includes a step of using a thick field device to establish the corresponding current path.