Digital signal processing for linearization of small input signals to a tri-state power switch

• US 5,617,058 A
• Filed: 11/13/1995
• Issued: 04/01/1997
• Est. Priority Date: 11/13/1995
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Apogen Technologies Incorporated (Perspecta, Inc.)
• Inventors: Spiegel, Leo, Danielson, Michael S., Adrian, Andrew A., Meyers, David B.
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US08/556,615
• Time in Patent Office: 505 Days
• Field of Search: 330/10, 330/146, 330/149, 330/207 A, 330/251
• US Class Current: 330/10
• CPC Class Codes: H03F 1/3264 in audio amplifiers
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 3/217 Class D power amplifiers; Switching amplifiers

Abstract

An all digital switching amplifier wherein linearization of the power switch is accomplished solely by using three states. A small, fixed width, bi-state compensating carrier waveform is added to the leading or training edges of an oversampled main input pulse producing a compensated composite waveform. This compensating carrier linearizes output from a power switch by effecting common mode cancellation of switch time errors. Output pulse width combinations for the compensating carrier are obtained from a look-up table stored in memory. A correction mechanism is implemented to correct for harmonic distortion that is dependent on the modulation level or index and results from the compensating carrier modulation. The correction mechanism applies the inverse of the modulation induced distortion to the oversampled compensated composite input signal to null distortion products resulting from the modulation scheme used to apply the small carrier to linearize the performance of the tri-state power switch. Digital timing control of the power switch'"'"'s deadband ensures accuracy of the timing and sequence in which individual switches within the power switch H-bridge are turned off and turned on, so as to preclude a short circuit across the power supply. A high speed clock used in linearizing the power switch provides a timing reference to generate the necessary deadband timing delays and pulse width increments. The output bridge uses enhancement mode MOSFETs.

Claims

1. A method for linearizing the output of at least one power switch having switch timing error in an amplifier receiving an input signal and providing a switched output signal, said method comprising the steps of:

producing a compensated composite waveform by modulating said input signal with a bi-state compensating pulse waveform; and

effecting common mode cancellation of said switch timing error by passing said compensated composite waveform through said at least one power switch having switch timing error to provide said switched output signal.

2. The method of claim 1 wherein said bi-state compensating pulse waveform includes a first state portion which is a function of switch timing error, and a second state portion having a minimum pulse width that is a function of said input signal and said switch timing error.

3. The method of claim 1 wherein said bi-state compensating waveform has a pulse width that is produced by accessing a lookup table in memory.

4. The method of claim 1 further including a step of pre-compensating said input signal by determining a modulation induced distortion and applying an inverse of said modulation induced distortion to said input signal.

5. The method of claim 4 wherein coefficients used to determine said inverse of said modulation induced distortion are stored in a look up table referenced by an estimated amplitude of said input signal.

6. The method of claim 1 wherein said at least one power switch comprises a plurality of power switches and said method further includes the step of:

controlling accuracy of timing and a sequence in which individual ones of said plurality of power switches are turned off and turned on to substantially avoid a short circuit of any duration across a power supply controlled by said plurality of switches.

7. The method of claim 1 wherein said at least one power switch comprises a plurality of power switches and said method further includes a step of:

processing a portion of said input signal to produce an oversampled input signal having a fixed length and a fixed frequency; and

controlling accuracy of timing and a sequence in which individual ones of said plurality of power switches are turned off and turned on to substantially avoid a short circuit of any duration across a power supply controlled by said plurality of switches.

8. The method of claim 7 wherein said step of controlling accuracy of timing and a sequence in which individual ones of said plurality of power switches are turned off and turned on, involves using a high speed digital clock to control timing and said sequence, said high speed digital clock being synchronous with said fixed frequency of said oversampled input signal.

9. The method of claim 1 wherein said at least one power switch comprises a plurality of power switches and each of said plurality of power switches comprises an enhancement mode MOSFET.

10. A tri-state digital switching amplifier receiving an input signal and having a plurality of output modes including a first mode, a second mode and a third mode, and providing a switched output signal, comprising:

a digital signal processor receiving said input signal and processing said input signal by modulating said input signal with a bi-state compensating pulse waveform to produce a compensated input signal;

at least one power switch including switch timing error and effecting switching between said first mode, said second mode and said third mode, said at least one power switch receiving said compensated input signal from said digital signal processor and outputting said compensated input signal in at least one of said first mode, said second mode and said third mode to provide said switched output signal substantially free of said switch timing error.

11. The tri-state digital switching amplifier of claim 10 wherein said bi-state compensating pulse waveform includes a first state portion which is a function of switch timing error, and a second state portion having a minimum pulse width that is a function of said input signal and said switch timing error.

12. The tri-state digital switching amplifier of claim 10 wherein said bi-state compensating waveform has a pulse width that is produced by accessing a lookup table in memory.

13. The tri-state digital switching amplifier of claim 10 wherein said digital signal processor includes a pre-compensation mechanism pre-compensating said input signal by determining a modulation induced distortion and applying an inverse of said modulation induced distortion to said input signal.

14. The tri-state digital switching amplifier of claim 13 further including a memory accessible by said digital signal processor and wherein coefficients used to determine said inverse of said modulation induced distortion are stored in a look up table in said memory referenced by an estimated amplitude of said input signal.

15. The tri-state digital switching amplifier of claim 10 wherein said at least one power switch comprises a plurality of power switches and said amplifier further includes a synchronization and timing control mechanism in communication with said plurality of power switches to control accuracy of timing and a sequence in which individual ones of said plurality of power switches are turned off and turned on to substantially avoid a short circuit across a power supply controlled by said plurality of switches.

16. The tri-state digital switching amplifier of claim 10 wherein said digital signal processor includes an input oversampling mechanism processing a portion of said input signal to produce an oversampled input signal having a fixed length and a fixed frequency and further including a synchronization and timing control mechanism in communication with said plurality of power switches to control accuracy of timing and a sequence in which individual ones of said plurality of power switches are turned off and turned on to substantially avoid a short circuit of any duration across a power supply controlled by said plurality of switches.

17. The tri-state digital switching amplifier of claim 16 wherein a high speed digital clock is used to control timing and said sequence, said high speed digital clock being synchronous with said fixed frequency of said oversampled input signal.

18. The tri-state digital switching amplifier of claim 10 wherein said at least one power switch comprises a plurality of power switches and each of said plurality of power switches comprises an enhancement mode MOSFET.