Method for estimating interconnect delays in integrated circuits

• US 5,617,325 A
• Filed: 09/04/1992
• Issued: 04/01/1997
• Est. Priority Date: 06/22/1990
• Status: Expired due to Fees

• Current Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Schaefer, Thomas J.
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US07/941,763
• Time in Patent Office: 1,670 Days
• Field of Search: 364/488, 364/489, 364/490, 364/578, 364/802, 371/23
• US Class Current: 716/104
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A method for predicting circuit interconnect delays in circuits of the type that have a driving device attached to an input node of a network having a plurality of nodes, with the driving device changing states from time to time so as to impose on the network a voltage different from the previous voltage of the network. The method includes the steps of estimating the waveform on the input node and predicting the waveforms on other nodes of the network on the basis of the estimated input node waveform.

Claims

1. For an original circuit having an original driving device connected to an original driving node and another node connected to said original driving node through an impedance network, a method of determining an approximate delay time after said original driving device is turned on at which a voltage at said another node reaches a predetermined value, comprising the steps of:

for a substitute circuit having a substitute driving device connected to a substitute driving node and specified by a predetermined set of parameters, determining for a multiplicity of different sets of values of said predetermined set of parameters, using a computer simulator, voltage waveforms expected at said substitute driving node in response to said substitute driving device being turned on, and retrievably storing discrete-time representations of said voltage waveforms;

determining a set of values of said predetermined set of parameters for which delay characteristics of said substitute circuit approximate delay characteristics of said original circuit, and from said discrete-time representations of said voltage waveforms, determining a voltage waveform corresponding to said set of values;

scaling said voltage waveform such that a resulting scaled voltage waveform approximates a voltage waveform expected at said original driving node of said original driving circuit in response to said original driving device being turned on;

determining an approximate analytical expression for said scaled voltage waveform; and

predicting said approximate delay time of said original circuit using said approximate analytical expression.

2. The method according to claim 1 wherein the impedence network is an RC network.

3. The method according to claim 2 wherein the RC network includes a plurality of nodes joined by at least one of linear resistors and distributed resistor and capacitor elements.

4. The method according to claim 1 wherein said original driving node is a macro-cell output pin and said another node is a macro-cell input pin.

5. The method according to claim 1 wherein the substitute circuit includes a linear resistance, a substitute driving node capacitance and an output node capacitance, and said predetermined set of parameters includes the values of the linear resistance, substitute driving node capacitance and output node capacitance.

6. The method according to claim 1 wherein the set of values of the predetermined set of parameters is determined by computing several electrical parameters of the network, and selecting the set of values so that the electrical parameters match the corresponding electrical parameters of the substitute circuit.

7. The method according to claim 6 wherein the impedance network is an RC network and the electrical parameters comprise a predetermined number of moment-weighted capacitances.

8. The method according to claim 7 wherein the number of the moment-weighted capacitances is three.

9. The method according to claim 8 wherein the output node capacitance of the substitute circuit, comprising the substitute driving node and an output node connected by a linear resistor, equals the square of the first-order moment-weighted capacitance divided by the second-order moment-weighted capacitance, the linear resistance of the substitute circuit equals the square of the second-order moment-weighted capacitance divided by the cube of the first-order moment-weighted capacitance, and the substitute driving node capacitance equals the zero-order moment-weighted capacitance minus the output node capacitance of the substitute circuit.

10. The method according to claim 1 wherein the step of determining an approximate analytical expression for the scaled voltage waveform produces a piecewise description of the scaled voltage waveform, wherein each piece spans some specified time interval and is described in terms of an analytic function.

11. The method according to claim 10 wherein the analytic function comprises at least one of a straight line, a simple exponential, and a polynomial.

12. The method according to claim 1 wherein the step of using the analytical expression to predict said delay time further includes determining the response of said another node to the scaled voltage waveform using a linear system solution.

13. The method according to claim 12 wherein the step of determining a response includes:

approximating said another node as a linear system having a number of time constants and associated parameters; and

determining a response of this linear system to the scaled voltage waveform.

14. The method according to claim 13 wherein the number of time constants is at least two.

15. The method according to claim 14 wherein the step of approximating further includes choosing the time constants and associated parameters to fit said another node.

16. The method according to claim 15 wherein the step of choosing includes computing several significant time constants of the original circuit, and selecting time constants and parameters for said another node based on the several computed time constants.

17. The method according to claim 16 wherein the step of choosing includes determining several significant time constants by computing a predetermined number of impulse response moments for said another node and choosing the time constants and associated parameters for said another node to provide moments which correspond to the impulse response moments.

18. The method according to claim 17 wherein the predetermined number of computed impulse response moments is at least two.

19. The method according to claim 17 wherein the number of impulse response moments is three, and the step of choosing includes the step of calculating the time constants for said another node by solving a quadratic equation.

20. The method according to claim 1 wherein the discrete time representations of said voltage waveforms are stored by constructing look-up tables using the results of the value determining step.

21. The method according to claim 20 wherein determining a voltage waveform corresponding to said set of values of said predetermined set of parameters includes the step of accessing a number of values from one or more look-up tables.

22. The method according to claim 21 wherein determining a voltage waveform corresponding to said set of values of said predetermined set of parameters includes the step of selecting a number of values from the look-up tables and interpolating between the selected values.

23. The method according to claim 22 wherein the values accessed from the look-up tables include values representing delays.

24. The method according to claim 22 wherein the substitute driving device belongs to a family of driving devices that can each be characterized by a real-number driver strength which indicates the speed with which the substitute driving device can drive a given capacitive load.