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Method for estimating interconnect delays in integrated circuits

  • US 5,617,325 A
  • Filed: 09/04/1992
  • Issued: 04/01/1997
  • Est. Priority Date: 06/22/1990
  • Status: Expired due to Fees
First Claim
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1. For an original circuit having an original driving device connected to an original driving node and another node connected to said original driving node through an impedance network, a method of determining an approximate delay time after said original driving device is turned on at which a voltage at said another node reaches a predetermined value, comprising the steps of:

  • for a substitute circuit having a substitute driving device connected to a substitute driving node and specified by a predetermined set of parameters, determining for a multiplicity of different sets of values of said predetermined set of parameters, using a computer simulator, voltage waveforms expected at said substitute driving node in response to said substitute driving device being turned on, and retrievably storing discrete-time representations of said voltage waveforms;

    determining a set of values of said predetermined set of parameters for which delay characteristics of said substitute circuit approximate delay characteristics of said original circuit, and from said discrete-time representations of said voltage waveforms, determining a voltage waveform corresponding to said set of values;

    scaling said voltage waveform such that a resulting scaled voltage waveform approximates a voltage waveform expected at said original driving node of said original driving circuit in response to said original driving device being turned on;

    determining an approximate analytical expression for said scaled voltage waveform; and

    predicting said approximate delay time of said original circuit using said approximate analytical expression.

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