Automatic code pattern generator for repetitious patterns in an integrated circuit layout

• US 5,617,328 A
• Filed: 05/23/1994
• Issued: 04/01/1997
• Est. Priority Date: 05/23/1994
• Status: Expired due to Term

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Huang, Kuo-Chih, Kuo, Mei-Ling, Tsai, Chiu-Mei
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Fiul, Dan
• Application Number:
  US08/248,068
• Time in Patent Office: 1,044 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 437/43, 178/19, 250/492.3
• US Class Current: 716/119
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

An automatic code pattern generator apparatus is disclosed which has a processor. The processor is for receiving a plurality of instructions including an instruction indicating a particular polygon specification associated with cells of at least one physical layer of a pre-programmed integrated circuit chip. The processor also receives at least one instruction indicating a regular ordered pattern of a plurality of the cells on the physical layers of the pre-programmed integrated circuit chip. The processor generates a code layer including a design of a layout of the polygons according to the regularly ordered pattern on the physical layers of the pre-programmed integrated circuit. The generated code layer also includes a mapping relationship between cell addresses, and corresponding ones of the cells associated with the polygons. The processor may also receive information indicating variations in particular addressed cells associated with the polygons of the regularly ordered pattern of cells. In response to this information, the processor modifies the design of the layout to include variations in the particular addressed cells, e.g., variations in the polygons associated with the particular addressed cells, according to the information.

Claims

1. An apparatus for generating a code layer physical layout of a pre-programmed device containing at least one two-dimensional array of addressed, identical cells to be varied comprising:

a processor which responds to;

(1) one or more instructions specifying a single, identical polygon to be associated with each addressed cell of a given one of said two-dimensional arrays, and

(2) at least one instruction specifying at least one two-dimensionally arrayed pattern of repetitions of said single polygon,

by forming a design of said code layer physical layout, said design formed by said processor locating said repetitions of said single polygon at specific locations of said given two-dimensional array, which locations are specified by said instructions,

said processor also generating a mapping relation, from said at least one instruction specifying said at least one two-dimensional arrayed pattern, which mapping relation relates each polygon of said design with the address of said associated addressed cell of said polygon.

2. The apparatus of claim 1 wherein said processor responds to said at least one instruction specifying said at least one two-dimensional arrayed pattern by regularly varying a spacing within a particular row or column direction of said two-dimensional arrayed pattern between adjacent polygons of said design.

3. The apparatus of claim 1 wherein said processor programs said pre-programmed device with a program containing one bit corresponding to each addressed cell by introducing a variation to said polygons of said design, wherein each polygon of said design associated with an addressed cell corresponding to the same logic bit value is varied in an identical manner.

4. The apparatus of claim 3 wherein said processor determines which polygon of said design to vary in programming said device by translating an address of a bit of said program using said mapping relation to a particular one of said polygons associated with a cell that corresponds to said translated address.

5. The apparatus of claim 1 wherein said processor merges said design of said layout with a design of a layout of other layers of said pre-programmed device to form a completed layout design.

6. The apparatus of claim 1 further comprising a fabrication device which fabricates at least part of said pre-programmed device according to said design of said layout.

7. The apparatus of claim 1 wherein said processor responds to instructions specifying:

(a) the number of cells in each row in the x direction of said layout,

(b) the number of cells in said x direction that correspond each data word addressed by each unique address,

(c) the number of rows of cells in the y direction of said layout and the number of sub-arrays into which said rows are organized, and

(d) a plurality of different regularly occurring spacings between cells within each row, between each row in each sub-array and between each sub-array,

by locating one polygon for each of said cells in each of said rows in each of said sub-arrays at locations that accord with said regularly occurring spacings.

8. A process for fabricating a code layer physical layout of a pre-programmed device containing at least one two-dimensional array of addressed, identical cells to be varied comprising the steps of:

(a) using a processor, receiving

(1) one or more instructions specifying a single, identical polygon to be associated with each addressed cell of a given one of said two-dimensional arrays, and

(2) at least one instruction specifying at least one two-dimensionally arrayed pattern of repetitions of said single polygon,

(b) using said processor, forming a design of said code layer physical layout, by locating said repetitions of said single polygon at specific locations of said given two-dimensional array, which locations are specified by said instructions, and

(c) generating a mapping relation, from said at least one instruction specifying said at least one two-dimensional arrayed pattern, which mapping relation relates each polygon of said design with the address of said associated addressed cell of said polygon.

9. The process of claim 8 further comprising the step of:

(d) using said processor, in response to said at least one instruction specifying said at least one two-dimensional arrayed pattern, regularly varying a spacing within a particular row or column direction of said two-dimensional arrayed pattern between adjacent polygons of said design.

10. The process of claim 8 further comprising the step of:

(d) using said processor, programming said pre-programmed device with a program containing one bit corresponding to each addressed cell by introducing a variation to said polygons of said design, wherein each polygon of said design associated with an addressed cell corresponding to the same logic bit value is varied in an identical manner.

11. The process of claim 10 further comprising the step of:

(e) using said processor, determining which polygon of said design to vary in programming said device by translating an address of a bit of said program using said mapping relation to a particular one of said polygons associated with a cell that corresponds to said translated address.

12. The process of claim 8 further comprising the step of:

(d) using said processor, merging said design of said layout with a design of a layout of other layers of said pre-programmed device to form a completed layout design.

13. The process of claim 8 further comprising the step of:

(d) fabricating at least part of said pre-programmed device according to said design of said layout.

14. The process of claim 8 further comprising the step of:

(d) using said processor, receiving instructions specifying;

(1) the number of cells in each row in the x direction of said layout,

(2) the number of cells in said x direction that correspond each data word addressed by each unique address,

(3) the number of rows of cells in the y direction of said layout and the number of sub-arrays into which said rows are organized, and

(4) a plurality of different regularly occurring spacings between cells within each row, between each row in each sub-array and between each sub-array, and

(e) using said processor, locating one polygon for each of said cells in each of said rows in each of said sub-arrays at locations that accord with said regularly occurring spacings.