Method and reference standards for measuring overlay in multilayer structures, and for calibrating imaging equipment as used in semiconductor manufacturing

• US 5,617,340 A
• Filed: 02/03/1995
• Issued: 04/01/1997
• Est. Priority Date: 04/28/1994
• Status: Expired due to Fees

• Current Assignee: THE GOVERNMENT OF THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCE
• Original Assignee: THE GOVERNMENT OF THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCE
• Inventors: Kopanski, Joseph J., Allen, Richard A., Cresswell, Michael W., Linholm, Loren W.
• Primary Examiner(s): Cosimano, Edward R.
• Assistant Examiner(s): COLE, TONY MITCHELL
• Application Number:
  US08/382,973
• Time in Patent Office: 788 Days
• Field of Search: 250/491.1, 257/48, 156/626.1, 156/627.1, 437/8, 324/719, 324/602, 324/765, 324/699, 324/691, 324/716, 348/87, 348/94, 348/95, 356/399, 356/394, 356/373, 364/559, 364/571.01, 364/579, 430/22, 430/30
• US Class Current: 702/85
• CPC Class Codes: G01R 31/2818 using test structures on, or modifications of, the card under test, made for the purpose of testing, e.g. additional components or connectors G01R31/2805 takes precedence; printed circuits having, e.g. symbols, test patterns or visualisation means H05K1/0266
• CPC Class Codes: G01R 31/303 of integrated circuits G01R31/305 - G01R31/315 take precedence
• CPC Class Codes: G01R 31/311 of integrated circuits G01R31/31728 takes precedence
• CPC Class Codes: G01R 35/005 Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references G01R33/0035, G01R35/002 take precedence
• CPC Class Codes: G03F 7/70591 Testing optical components
• CPC Class Codes: G03F 7/70616 Monitoring the printed patterns
• CPC Class Codes: G03F 7/70633 Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: H01C 10/06 adjustable by short-circuiting different amounts of the resistive element
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

Imaging instruments for inspecting products, such as semiconductor chips, are calibrated by providing a reference test structure having features which can be located by electrical measurements not subject to tool-induced shift and wafer-induced shift experienced by the imaging instrument. The reference test structure is first qualified using electrical measurements, and is then used to calibrate the imaging instrument. The electrical measurements may be made by forcing a current between a plurality of spaced reference features and an underlying conductor, or may be made by capacitive, conductive, magnetic, or impedance-measuring techniques. Capacitive techniques may also be used to detect features not susceptible of resistance measurement, such as dielectric or insulative materials, or metallic structures not accessible for forcing a current therethrough. A series of test structure elements may be fabricated with one component of each being spaced at progressively greater distances from an arbitrary baseline, such that a null-overlay element may be identified.

Claims

1. A method for calibrating an imaging instrument with respect to measurements of distance between features of a structure formed in a sequence of steps on a substrate, measurements made by said imaging instrument being susceptible to one or both of tool-induced shift (TIS) and wafer-induced shift (WIS), comprising the steps of:

forming a structure comprising components formed in a sequence of steps on a substrate, said components of said structure each comprising first artifacts the spacing of which is measurable using said imaging instrument, and also comprising second artifacts the spacing of which is analyzable using electrical measurement techniques not susceptible to TIS or WIS, said first and second artifacts being in defined physical relation to one another;

measuring the spacing of said first artifacts employing said imaging instrument;

analyzing the spacing of said second artifacts employing said electrical measurement technique; and

calibrating said imaging instrument responsive to comparison of said measurements and analyses.

2. The method of claim 1, wherein said step of forming a structure on a substrate comprises the steps of:

providing a substrate;

forming a first patterned conductive layer on said substrate in a first fabrication step, said first layer being patterned to define reference members detectable by said imaging instrument to be calibrated, and further defining a number of test points in fixed spatial relation to said reference members; and

forming a second layer of a second material overlying said first layer in a subsequent fabrication step, said second layer being patterned to define reference marks detectable by said imaging instrument for measurement of the relation thereof to said reference members defined by said first layer, and to further define a series of features spaced successively greater distances from a baseline in fixed spatial relation to said reference marks;

said features being such that the positions of the features with respect to said test points are determinable employing an electrical technique;

wherein said step of measuring the spacing of said first artifacts employing said imaging instrument comprises the step of measuring the spatial relation of the reference marks with respect to the reference members employing said imaging instrument;

wherein said step of analyzing the spacing of said second artifacts employing said electrical measurement technique comprises the step of performing a series of electrical measurements with respect to each of said features, wherein said electrical measurements provide a measured value corresponding to the degree of alignment of each feature to an underlying test point, and comparing the electrically-measured values in order to determine which of the features most closely approaches a predetermined relation to the corresponding test point, to provide a value for the spatial relation of the first and second layers not affected by TIS or WIS; and

wherein said step of calibrating said imaging instrument responsive to comparison of said measurements and analyses is performed by comparing the measurement of the spacing of the reference marks with respect to the reference members made employing said imaging instrument to the value for the spatial relation of the first and second layers not affected by TIS or WIS made using said electrical technique.

3. The method of claim 2, wherein said test points defined by said first layer are points spaced along an elongated conductor extending substantially parallel to said baseline, and said features defined by said second layer of said second material comprise conductive members overlying said elongated conductor, such that the alignment of said features is determined by measuring the resistance between the conductive members and theunderlying conductor.

4. The method of claim 1, wherein said imaging instrument is an optical microscope.

5. The method of claim 1, wherein said imaging instrument is an electron microscope.

6. The method of claim 1, wherein said electrical measurement technique comprises the steps of forcing a current through physically contacting electrically conducting portions of said structure, and measuring the resistance therebetween, in order to evaluate the degree of alignment of said portions.

7. The method of claim 1, wherein said electrical measurement technique comprises the steps of disposing a probe in close juxtaposition to said structure, applying a test signal between said probe and said portions of said structure, and measuring one or more of the relative capacitance, inductance, or impedance therebetween, in order to evaluate the degree of alignment of said portions.

8. A method for calibrating optical measurements of overlay exhibited with respect to successive steps in fabrication of a multiple-layer planar product, comprising the steps of:

providing a test structure comprising;

a substrate;

a first conductive layer, formed on said substrate in a first fabrication step, and patterned to define optically-detectable reference members, and to further define a number of test point locations in fixed spatial relation to said reference members; and

a second layer of a second material formed overlying said first layer in a subsequent fabrication step, said second layer being patterned to define optically-detectable reference marks for optical measurement of the relation thereof to said reference members defined by said first layer, and to further define a series of features spaced successively greater distances from a baseline in fixed spatial relation to said reference marks;

said features being such that the positions of the features with respect to said test points are determinable employing an electrical technique;

optically measuring the spatial relation of the reference marks with respect to the reference members, to derive an optically-measured value for overlay of the first and second layers;

performing a series of electrical measurements with respect to each of said features, to derive a series of electrically-measured values for overlay, each responsive to the degree of alignment of the corresponding feature to an underlying test point;

comparing the series of electrically-measured values in order to identify a null-overlay feature most closely approaching a predetermined relation to the corresponding test point; and

correcting the optically-measured value for the overlay accordingly.

9. The method of claim 8, comprising the further steps of forming at least one such test structure at each of a plurality of exposure sites on a single substrate, and stepping a tool used to form the second layer of each test structure at each exposure site between successive exposure sites prior to each of the subsequent fabrication steps.

10. The method of claim 8, wherein at least three such test structures are formed at each of said plurality of exposure sites on a single substrate, said tool being used to form the second layer of each test structure simultaneously at each exposure site.

11. The method of claim 10, comprising the further step of analyzing the electrically-measured values indicating which of the features most closely approaches a predetermined relation to the corresponding test point with respect to each test structure formed at each exposure site in order to discriminate between tool-induced shift, wafer-induced shift, and other sources of error in fabrication of said layers.

12. The method of claim 8, wherein said first layer is patterned to define an elongated conductor extending substantially parallel to said baseline, and said features defined by said second layer of said second material comprise conductive members overlying said elongated conductor at spaced test point locations therealong.

13. The method of claim 12, wherein said conductive members directly contact the underlying elongated conductor, and wherein said step of electrical measurement is performed by successively forcing a current between each of the conductive members and the underlying conductor and measuring the electrical resistance therebetween.

14. The method of claim 13, wherein said step of comparing the series of electrically-measured values in order to identify a null-overlay feature is performed by comparing the resistances thus measured, and selecting the conductive region exhibiting the minimal resistance with respect to the underlying conductor as the null-overlay feature.

15. The method of claim 8, wherein said first layer is patterned to define an elongated conductive member parallel to said baseline, and wherein said features of said second layer define the locations of conductive members contacting said elongated conductive member at said successively greater distances from said baseline.

16. The method of claim 15, wherein said step of performing a series of electrical measurements with respect to each of said features is performed by successively forcing a current between said conductive members and said elongated conductor, and measuring the resistance therebetween.

17. The method of claim 15, wherein said first layer is further patterned to define a series of transverse conductive members at said test point locations along said elongated conductor, and wherein said step of performing a series of electrical measurements with respect to each of said features is performed by successively forcing a current between said conductive members and said elongated conductor, and measuring a voltage between the ends of the corresponding transverse members.

18. The method of claim 17, wherein said step of performing a series of electrical measurements with respect to each of said features is performed by successively forcing a current between said conductive members and said elongated conductor, and measuring differential voltages between the ends of the transverse members and the center thereof.

19. The method of claim 8, wherein said first layer is patterned to define an elongated conductive member parallel to said baseline, and wherein each of said features comprises two conductive members defined by said second layer at each of said test points, said two conductive members of each feature being spaced from one another in a direction perpendicular to said baseline by a distance less than the width of said elongated conductive member, such that both said conductive members of a null-overlay feature contact said elongated conductive member.

20. The method of claim 8, wherein said test points defined by said first layer are spaced along an elongated conductor extending substantially parallel to said baseline, and said features defined by said second layer of said second material comprise features formed in dielectric material overlying said elongated conductor at spaced locations therealong.

21. The method of claim 20, wherein said step of electrical measurement is performed by applying an electrical test signal to each of the features, and measuring one of the electrical resistance, capacitance, inductance, or impedance between the feature and the underlying conductor.

22. The method of claim 21, wherein said step of comparing the series of electrically-measured values in order to identify a null-overlay feature is performed by comparing the measured values for the electrical resistance, capacitance, inductance, or impedance.

23. A test structure enabling calibration of imaging instruments for measurement of overlay as experienced during fabrication of products formed in multiple-step processes, measurements of overlay as made by such imaging instruments being susceptible to one or both of tool-induced shift (TIS) and wafer-induced shift (WIS), said structure comprising a first component formed in a first step and at least a second component formed in a second step, said first and second components together defining a number of artifacts on said substrate, an electrical characteristic of each of said artifacts varying in accordance with the relative alignment of the first and second components thereof, such that the relative alignment of said first and second components comprised by each of said artifacts are measurable using said imaging instrument to be calibrated and using electrical measurement techniques not susceptible to TIS and WIS.

24. The test structure of claim 23, wherein said artifacts each comprise:

a first conductive layer, formed on a substrate in a first fabrication step, and patterned to define reference members detectable employing an imaging instrument; and

a second layer of a second material formed overlying said first conductive layer in a subsequent fabrication step, said second layer being patterned to define reference marks detectable by said imaging instrument, for measurement of the relation thereof to said reference members defined by said first conductive layer employing said imaging instrument to be calibrated,

said first and second layers collectively defining a series of features, each feature being space a successively greater distance from a baseline fixed with respect to said reference marks; and

wherein the position of each feature with respect to said baseline is determinable employing an electrical technique.

25. The test structure of claim 24, wherein the position of one of first and second members of each feature varies with respect to said baseline, and wherein an electrical characteristic of each feature may be measured to identify a null-overlay feature.

26. The test structure of claim 25, wherein the material of said second layer is conductive, and wherein said features defined collectively by said first and second layers comprise first and second members in electrical contact with one another, such that the measured electrical characteristic of each feature is the resistance therebetween.

27. The test structure of claim 25, wherein the material of said second layer is a dielectric, and wherein the relation of members of said features defined by said second layer with respect to members thereof defined by said underlying conductive layer can be determined using a non-contacting electrical technique.

28. The test structure of claim 27, wherein said non-contacting electrical technique comprises applying a test signal at intervals across the surface of said structure, and monitoring variation in the capacitance, impedance, or inductance exhibited thereby as a function of position.

29. The test structure of claim 28, wherein the relative alignment of said first and second components of said artifacts is determined by measurement of the capacitance, impedance, or inductance therebetween.

30. A test structure for null-overlay detection, comprising a number of test structure elements, each test structure element comprising a first-formed member and a second-formed member, wherein one of each of the first-formed and second-formed members of each test structure element is located in fixed relation to a baseline and the other of each of the first-formed and second-formed members of each test structure element is spaced a progressively greater distance from said baseline in a direction perpendicular thereto, and wherein the relative alignment of said first-formed and second-formed members of each test structure element may be evaluated to identify one thereof as a null-overlay test structure element.

31. The test structure of claim 30, wherein said first- and second-formed members are conductive, and the relative alignment thereof is evaluated by measuring the electrical resistance therebetween.

32. The test structure of claim 31, wherein said second-formed members are located by formation in vias in insulative members disposed over said first-formed members.

33. The test structure of claim 32, wherein said first-formed members of each test structure element are defined by an elongated conductor extending generally parallel to said baseline.

34. The test structure of claim 33, wherein said first-formed member of each test structure element further defines a conductive element extending transverse to said elongated conductor.

35. The test structure of claim 33, wherein said second-formed members of each test structure element each comprise a pair of conductive members spaced from one another in a direction perpendicular to said baseline by a gap of width less than the width of said elongated conductor.

36. The test structure of claim 30, wherein said first-formed member of each test structure comprises an elongated bridge conductor having a plurality of taps connected thereto for measuring voltages therebetween responsive to a current forced along said bridge conductor, each test structure element further comprising a second-formed conductor connected to said bridge conductor.