Fixed coefficient high decimation filter

• US 5,617,344 A
• Filed: 06/01/1995
• Issued: 04/01/1997
• Est. Priority Date: 08/14/1992
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Chester, David B., Young, William R.
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US08/457,234
• Time in Patent Office: 670 Days
• Field of Search: 364/724.1, 364/754, 364/757
• US Class Current: 708/313
• CPC Class Codes: H03D 7/165 at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002
• CPC Class Codes: H03H 17/06 Non-recursive filters
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00
• CPC Class Codes: H04B 1/0021 Decimation, i.e. data rate reduction techniques H04B1/0025 takes precedence
• CPC Class Codes: H04B 1/26 for superheterodyne receivers multiple frequency-changing H03D7/16
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22
• CPC Class Codes: H04J 1/05 using digital techniques
• CPC Class Codes: H04Q 11/04 for time-division multiplexing H04Q11/0001 takes precedence

Abstract

A digital down converter with a programmable mixing down frequency and a programmable extraction bandwidth uses a ROM based sin/cos generator plus a programmable high decimation filter followed by a gain compensating scaling multiplier and a fixed FIR filter. Output format options are also programmable, and programming commands are serially loaded into registers. Various components may be isolated for efficient testing and also subsystem operation.

Claims

1. A digital filter, comprising:

(a) a decimation filter with a first filter input, a first filter output, and an adjustable decimation rate input, with the decimation rate of said decimation filter dependent upon said decimation rate input and with the gain of said decimation filter dependent upon said decimation rate;

(b) a multiplier with a multiplier input, a multiplicand input, and a product output, said multiplicand input coupled to said first filter output and said multiplier input with the reciprocal of said gain; and

(c) a fixed coefficient filter with second filter input coupled to said product output and with a second filter output.

2. The filter of claim 1, further comprising:

(a) a second decimation filter with a third filter input, a third filter output, and with said decimation rate and said gain;

(b) a second multiplier with a second multiplier input, a second multiplicand input, and a second product output, said second multiplicand input coupled to said third filter output and said multiplier input with said reciprocal of said gain; and

(c) a second fixed coefficient filter with fourth filter input coupled to said second product output and with a fourth filter output.

3. The filter of claim 1, further comprising:

(a) a second decimation filter with a third filter input, a third filter output, and with said decimation rate and said gain;

(b) a second multiplicand input and a second product output for said multiplier, said second multiplicand input coupled to said third filter output, wherein said multiplier includes a multiplexer for alternating multiplications of data at said first and second multiplicand inputs which are output at said first and second product outputs, respectively; and

(c) a second fixed coefficient filter with fourth filter input coupled to said second product output and with a fourth filter output.

4. The filter of claim 3, wherein:

(a) said multiplier includes Wallace trees and a recoder coupled to said multiplicand inputs.

5. A digital filter, comprising:

a decimation filter with a first filter input, a first filter output, and an adjustable input decimation rate, and with the gain of said decimation filter dependent upon said decimation rate;

a multiplier with a multiplier input, a multiplicand input, and a product output, said multiplicand input coupled to said first filter output and said multiplier providing gain compensation; and

a fixed coefficient filter with second filter input coupled to said product output and with a second filter output.

6. The filter of claim 5 further comprising:

a second decimation filter with a third filter input, a third filter output, and with said decimation rate and said gain;

a second multiplier with a second multiplier input, a second multiplicand input, and a second product output, said second multiplicand input coupled to said third filter output and said multiplier providing gain compensation; and

a second fixed coefficient filter with fourth filter input coupled to said second product output and with a fourth filter output.

7. The filter of claim 5, further comprising:

a second decimation filter with a third filter input, a third filter output, and with said decimation rate and said gain;

a second multiplicand input and a second product output for said multiplier, said second multiplicand input coupled to said third filter output, wherein said multiplier includes a multiplexer for alternating multiplications of data at said first and second multiplicand inputs which are output at said first and second product outputs, respectively; and

a second fixed coefficient filter with fourth filter input coupled to said second product output and with a fourth filter output.

8. The filter of claim 7, wherein:

said multiplier includes Wallace trees and a recoder coupled to said multiplicand inputs.

9. A digital filter, comprising:

a decimation filter with a first filter input, a first filter output, and an adjustable decimation rate input;

a multiplier with a multiplier input, a multiplicand input, and a product output, said multiplicand input coupled to said first filter output; and

a fixed coefficient filter with second filter input coupled to said product output and with a second filter output.

10. The filter of claim 9 wherein said decimation filter said gain varies between 0.5 (exclusive) and 1 (inclusive).

11. The filter of claim 9 wherein said multiplicand input is coupled to said first filter output and said multiplier input and is responsive to said gain.

12. The filter of claim 9 wherein said decimation filter further comprises a fixed word length.