Three-dimensional direct-write EEPROM arrays and fabrication methods

• US 5,617,351 A
• Filed: 06/05/1995
• Issued: 04/01/1997
• Est. Priority Date: 03/12/1992
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: DiMaria, Donelli J., Bertin, Claude L., Miyakawa, Makoto, Sakaue, Yoshinori
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US08/464,018
• Time in Patent Office: 666 Days
• Field of Search: 365/185.01, 365/185.08, 365/185.05, 365/185.14, 365/149, 365/195, 257/298, 257/302, 257/319, 257/320
• US Class Current: 365/185.05
• CPC Class Codes: H01L 29/7882 charging by injection of carriers through a conductive insulator, e.g. Poole-Frankel conduction
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A three-dimensional memory cell, suitable for electrically erasable programmable read only memories (EEPROMS), which has direct-write cell capability is disclosed. The memory cell is utilized in the fabrication of non-volatile, direct-write EEPROM arrays with high integration density. A typical EEPROM array includes a plurality of elongated shallow trenches formed in a semiconductor substrate. Multiple direct-write EEPROM cells are disposed within each elongated trench such that each EEPROM cell shares a recall gate and a program gate with another cell in the same trench. Preferably, a silicon rich dielectric (such as silicon rich oxide) disposed between each floating gate and its associated programming and recall gates. Both common source diffusion and isolated source diffusion embodiments are disclosed. Further, various fabrication methods for the direct-write EEPROM arrays presented are described.

Claims

1. A direct-write EEPROM memory array formed in a semiconductor substrate, said memory array comprising:

a first elongated trench formed in the semiconductor substrate;

multiple vertical direct-write EEPROM cells disposed in said first elongated trench, one of said EEPROM cells being paired within said first elongated trench with another of said EEPROM cells such that paired EEPROM cells are disposed in said first elongated trench, the paired EEPROM cells being disposed on respective opposing walls of the elongated trench; and

at least one control gate disposed within said first elongated trench, said paired EEPROM cells sharing a control gate of said at least one control gate, at least a portion of the shared control gate of said at least one control gate comprising a single electrically continuous gate structure disposed in the trench between, and in operative relationship with, the paired EEPROM cells, the shared control gate of the at least one control gate being in electrical contact with a line structure crossing the first elongated trench to thereby operate each EEPROM cell of the paired EEPROM cells; and

an electrically continuous diffusion structure associated with said first elongated trench, said electrically continuous diffusion structure comprising either a source node or a drain node for each of at least two vertical direct-write EEPROM cells of said multiple vertical direct-write EEPROM cells disposed in said first elongated trench.

2. The direct-write EEPROM memory array of claim 1, further comprising:

a plurality of substantially parallel, elongated trenches adjacently formed in the semiconductor substrate, said plurality of elongated trenches including said first elongated trench; and

a plurality of vertical EEPROM cells disposed within said plurality of elongated trenches, multiple vertical EEPROM cells being disposed within each of said plurality of elongated trenches.

3. The direct-write EEPROM memory array of claim 2, wherein:

each of said multiple EEPROM cells disposed in each of said plurality of elongated trenches is paired with another of said EEPROM cells disposed in the same elongated trench such that EEPROM cell pairs are disposed in said plurality of elongated trenches; and

a plurality of discrete control gates are disposed within said plurality of elongated trenches, each control gate being shared by one of said EEPROM cell pairs.

4. The direct-write EEPROM memory array of claim 2, wherein each vertical EEPROM cell is configured to share a common diffusion with an EEPROM cell in an adjacent elongated trench.

5. The direct-write EEPROM memory array of claim 3, wherein each of said multiple vertical EEPROM cells in each of said elongated trenches shares a common diffusion with an EEPROM cell in an adjacent trench.

6. The direct-write EEPROM memory array of claim 1, wherein said EEPROM cells require an external voltage supply to be programmed, said external voltage supply being less than six volts.

20. The direct-write EEPROM memory array of claim 1, wherein the crossing line structure comprises at least a portion of a word line of said EEPROM memory array.

21. The direct-write EEPROM memory array of claim 20, wherein the electrically continuous diffusion structure comprises at least a portion of a bit line of said EEPROM memory array.

7. A memory cell array formed relative to a surface of a semiconductor substrate, said memory cell array comprising:

at least two elongated, substantially parallel adjacent trenches formed relative to said surface of said substrate, each of said elongated trenches having a bottom portion, first and second side portions, and a top portion;

at least two first electrodes, each of said first electrodes being elongated and disposed at said bottom portion of one of said elongated trenches such that each trench contains a first electrode, each of said first electrodes having a first surface portion;

at least two second electrodes, each of said second electrodes being disposed at said first side portion of one of said elongated trenches such that each trench contains a second electrode, each of said second electrodes having a second surface portion disposed adjacent said first surface portion of a respective one of said first electrodes for receiving injected electrons therefrom, and each of said second electrodes having a third surface portion;

at least two third electrodes, each of said third electrodes being disposed at said second side portion of one of said elongated trenches such that each trench contains a third electrode, each of said third electrodes having a second surface portion disposed adjacent said first surface portion of a respective one of said first electrodes for receiving injected electrons therefrom, and each of said third electrodes having a third surface portion;

at least two fourth electrodes, each of said fourth electrodes being disposed at said upper portion of one of said elongated trenches such that each trench contains a fourth electrode, each of said fourth electrodes being an electrically continuous gate structure disposed between, and in operative relationship with, a respective pair of second and third electrodes, each of said fourth electrodes having a fourth surface portion disposed adjacent said third surface portions of respective ones of said second and third electrodes for receiving electrons injected therefrom, each of said fourth electrodes being in electrical contact with a line structure crossing the two elongated trenches; and

an elongated diffusion region, said diffusion region being disposed between adjacent ones of said at least two elongated trenches, said elongated diffusion region being coupled to a signal source.

8. The memory cell array of claim 7, wherein:

a plurality of elongated, substantially parallel adjacent trenches are formed relative to said surface of said substrate, each of said elongated trenches having a bottom portion, first and second side portions, and a top portion; and

a plurality of first electrodes, second electrodes, third electrodes and fourth electrodes are provided, each of said plurality of first electrodes, second electrodes, third electrodes and fourth electrodes being associated with one of said plurality of elongated trenches.

9. The memory cell array of claim 8, wherein each of said plurality of trenches comprises a shallow trench formed in said surface of said substrate.

10. The memory cell array of claim 8, wherein said memory cell comprises an EEPROM cell and said first electrodes comprise recall gates, said second electrodes and said third electrodes comprise floating gates and said fourth electrodes comprise program gates.

11. The memory cell array of claim 10, wherein each of said plurality of elongated trenches includes multiple second electrodes disposed at said first side portion of said trench and multiple third electrodes disposed at said second side portion of said trench, each of said second electrodes being paired with one of said third electrodes.

12. The memory cell array of claim 11, wherein each of said plurality of elongated trenches includes multiple fourth electrodes, each of said fourth electrodes being associated with one of said second electrode and third electrode pairs.

13. The memory cell array of claim 12, further comprising a plurality of interconnection lines disposed above and orthogonal to said plurality of elongated trenches, the plurality of interconnection lines including the crossing line structures, each of said plurality of interconnection lines being coupled to respective ones of said plurality of fourth electrodes disposed therebeneath.

14. The memory cell array of claim 13, wherein said plurality of interconnection lines comprise wordlines and said elongated diffusion regions comprise bitlines, said wordlines and said bitlines allowing access to selected memory cells in said array.

15. The memory cell array of claim 8, wherein at least one elongated diffusion region pair is provided, each of said elongated diffusion region pairs comprising two distinct elongated diffusion regions, and each of said diffusion region pairs being disposed between adjacent ones of said at least two elongated trenches, each of said distinct elongated diffusion regions being coupled to a separate signal source.

16. The memory cell array of claim 15, wherein said two separate elongated diffusion regions of each of said diffusion region pairs are separated by an oxide isolation.

17. The memory cell array of claim 7, wherein each of said second electrodes and said third electrodes comprises an isolated floating gate.

18. The memory cell array of claim 17, wherein said second electrodes and said third electrodes are each partially isolated from a corresponding one of said first electrodes by a silicon rich nitride or a silicon rich oxide.

19. The memory cell array of claim 16, wherein said second electrodes and said third electrodes are each partially isolated from a corresponding one of said fourth electrodes by a silicon rich dielectric.

22. The memory cell array of claim 18, wherein the array requires a voltage supply to be programmed, said voltage supply being less than six volts.

23. The memory cell array of claim 19, wherein the array requires a voltage supply to be programmed, the voltage supply being less than six volts.