Three-dimensional direct-write EEPROM arrays and fabrication methods
First Claim
1. A direct-write EEPROM memory array formed in a semiconductor substrate, said memory array comprising:
- a first elongated trench formed in the semiconductor substrate;
multiple vertical direct-write EEPROM cells disposed in said first elongated trench, one of said EEPROM cells being paired within said first elongated trench with another of said EEPROM cells such that paired EEPROM cells are disposed in said first elongated trench, the paired EEPROM cells being disposed on respective opposing walls of the elongated trench; and
at least one control gate disposed within said first elongated trench, said paired EEPROM cells sharing a control gate of said at least one control gate, at least a portion of the shared control gate of said at least one control gate comprising a single electrically continuous gate structure disposed in the trench between, and in operative relationship with, the paired EEPROM cells, the shared control gate of the at least one control gate being in electrical contact with a line structure crossing the first elongated trench to thereby operate each EEPROM cell of the paired EEPROM cells; and
an electrically continuous diffusion structure associated with said first elongated trench, said electrically continuous diffusion structure comprising either a source node or a drain node for each of at least two vertical direct-write EEPROM cells of said multiple vertical direct-write EEPROM cells disposed in said first elongated trench.
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Accused Products
Abstract
A three-dimensional memory cell, suitable for electrically erasable programmable read only memories (EEPROMS), which has direct-write cell capability is disclosed. The memory cell is utilized in the fabrication of non-volatile, direct-write EEPROM arrays with high integration density. A typical EEPROM array includes a plurality of elongated shallow trenches formed in a semiconductor substrate. Multiple direct-write EEPROM cells are disposed within each elongated trench such that each EEPROM cell shares a recall gate and a program gate with another cell in the same trench. Preferably, a silicon rich dielectric (such as silicon rich oxide) disposed between each floating gate and its associated programming and recall gates. Both common source diffusion and isolated source diffusion embodiments are disclosed. Further, various fabrication methods for the direct-write EEPROM arrays presented are described.
210 Citations
23 Claims
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1. A direct-write EEPROM memory array formed in a semiconductor substrate, said memory array comprising:
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a first elongated trench formed in the semiconductor substrate; multiple vertical direct-write EEPROM cells disposed in said first elongated trench, one of said EEPROM cells being paired within said first elongated trench with another of said EEPROM cells such that paired EEPROM cells are disposed in said first elongated trench, the paired EEPROM cells being disposed on respective opposing walls of the elongated trench; and at least one control gate disposed within said first elongated trench, said paired EEPROM cells sharing a control gate of said at least one control gate, at least a portion of the shared control gate of said at least one control gate comprising a single electrically continuous gate structure disposed in the trench between, and in operative relationship with, the paired EEPROM cells, the shared control gate of the at least one control gate being in electrical contact with a line structure crossing the first elongated trench to thereby operate each EEPROM cell of the paired EEPROM cells; and an electrically continuous diffusion structure associated with said first elongated trench, said electrically continuous diffusion structure comprising either a source node or a drain node for each of at least two vertical direct-write EEPROM cells of said multiple vertical direct-write EEPROM cells disposed in said first elongated trench. - View Dependent Claims (2, 3, 4, 5, 6, 20, 21)
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7. A memory cell array formed relative to a surface of a semiconductor substrate, said memory cell array comprising:
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at least two elongated, substantially parallel adjacent trenches formed relative to said surface of said substrate, each of said elongated trenches having a bottom portion, first and second side portions, and a top portion; at least two first electrodes, each of said first electrodes being elongated and disposed at said bottom portion of one of said elongated trenches such that each trench contains a first electrode, each of said first electrodes having a first surface portion; at least two second electrodes, each of said second electrodes being disposed at said first side portion of one of said elongated trenches such that each trench contains a second electrode, each of said second electrodes having a second surface portion disposed adjacent said first surface portion of a respective one of said first electrodes for receiving injected electrons therefrom, and each of said second electrodes having a third surface portion; at least two third electrodes, each of said third electrodes being disposed at said second side portion of one of said elongated trenches such that each trench contains a third electrode, each of said third electrodes having a second surface portion disposed adjacent said first surface portion of a respective one of said first electrodes for receiving injected electrons therefrom, and each of said third electrodes having a third surface portion; at least two fourth electrodes, each of said fourth electrodes being disposed at said upper portion of one of said elongated trenches such that each trench contains a fourth electrode, each of said fourth electrodes being an electrically continuous gate structure disposed between, and in operative relationship with, a respective pair of second and third electrodes, each of said fourth electrodes having a fourth surface portion disposed adjacent said third surface portions of respective ones of said second and third electrodes for receiving electrons injected therefrom, each of said fourth electrodes being in electrical contact with a line structure crossing the two elongated trenches; and an elongated diffusion region, said diffusion region being disposed between adjacent ones of said at least two elongated trenches, said elongated diffusion region being coupled to a signal source. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 22, 23)
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Specification