Sign bit integrator and method

• US 5,617,473 A
• Filed: 06/23/1995
• Issued: 04/01/1997
• Est. Priority Date: 06/23/1995
• Status: Expired due to Term

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Wietecha, Stanley F., Olmstead, John A.
• Primary Examiner(s): Matar, Ahmad F.
• Assistant Examiner(s): KUMAR, DEVENDRA
• Application Number:
  US08/493,454
• Time in Patent Office: 648 Days
• Field of Search: 364/829, 364/833, 364/839, 364/840, 379/386, 379/399, 379/414, 341/118, 341/135, 327/336, 327/341, 327/307, 375/327, 333/19
• US Class Current: 379/399.02
• CPC Class Codes: H03M 1/0607 Offset or drift compensation removal of offset already present on the analogue input signal H03M1/1295
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H04M 1/253 Telephone sets using digital voice transmission

Abstract

A sign bit integrator and method for generating a signal to correct an offset in a signal processing system that can distort the output from the system. A charge pulse is generated when the sign of a input signal is sampled in order to provide an offset correction signal with a polarity opposite that of offsets in the system. The charge pulse is provided to a pair of transistors whose size ratio sets the magnitude of the charge pulse. The polarity of the charge pulse is set responsive to a sign bit in the input signal. An integrator capacitor provides the offset correction signal to the signal processing system. A third transistor may be switchably substituted for one of the pair of transistors to change the ratio of sizes and thus change the magnitude of the charge pulse to thereby change the speed with which the offset correction is made. The sign bit integrator and method may be used to correct distortion in a voice signal in a telephone system.

Claims

1. A sign bit integrator for generating a signal for correcting an offset in a signal processing system comprising:

an inverter for generating a periodic output;

a load capacitor for generating a charge pulse upon receipt of the output from said inverter;

circuit means comprising three or more transistors of different sizes and a switch for connecting two of said transistors to said load capacitor for changing the magnitude of the charge pulse by a ratio of sizes of the connected two of said transistors;

a sign bit receptor connected to said circuit means for setting a polarity of the charge pulse responsive to a sign bit signal; and

an integrator capacitor for receiving the charge pulse as set by said circuit means and said sign bit receptor,

whereby an output from said integrator capacitor is a signal for correcting an offset in the signal processing system.

2. The sign bit integrator of claim 1 wherein the ratio of sizes of a first pair of said three transistors is larger than the ratio of sizes of a second pair of said three transistors, whereby said first pair of transistors provide a faster correction of the offset.

3. A sign bit integrator for generating a signal for correcting distortion in a voice signal in a telephone system CODEC comprising:

an inverter for generating an output when a voice signal is sampled in a telephone system CODEC;

a load capacitor for generating a charge pulse upon receipt of the output from said inverter;

a current mirror connected to said load capacitor for selecting a magnitude of the charge pulse, said current mirror comprising plural transistors wherein a ratio of sizes of two of said plural transistors defines the magnitude of the charge pulse;

a sign bit receptor connected to said current mirror for setting a polarity of the charge pulse responsive to a sign bit signal in the voice signal; and

an integrator capacitor for receiving the charge pulse as changed by said current mirror and said sign bit receptor and for providing an output to the CODEC,

whereby the output from said integrator capacitor is a signal for correcting a distortion causing offset in the CODEC.

4. The sign bit integrator of claim 3 wherein said current mirror further comprises a switch for selecting the two transistors that define the magnitude of the charge pulse from among said plural transistors.

5. A sign bit integrator for generating a signal of selectable size for correcting an offset in a signal processing system comprising:

sampling means for periodically generating a charge pulse;

a current mirror connected to said sampling means for setting a magnitude of the charge pulse, said current mirror comprising,

plural transistors having different size active areas,

a switch for selecting two of said plural transistors, said selected transistors having a ratio of sizes that defines the magnitude of the charge pulse,

a sign bit receptor connected between said selected transistors for setting a polarity of the charge pulse responsive to a sign bit signal; and

output means connected to said current mirror for providing a signal for correcting an offset in the signal processing system.

6. The sign bit integrator of claim 5 wherein said plural transistors are in an integrated circuit and have active areas of the same length and unequal widths.

7. The sign bit integrator of claim 5 wherein said sampling means comprises an inverter for generating an output when a voice signal is sampled in a telephone system CODEC, and a load capacitor for generating the charge pulse upon receipt of the output from said inverter.

8. The sign bit integrator of claim 7 wherein said output means comprises an integrator capacitor for receiving the charge pulse as set by said current mirror and said sign bit receptor and for providing an output to the CODEC.

9. A method of generating a signal for reducing distortion in a voice signal in a telephone system CODEC comprising the steps of:

(a) generating a charge pulse when a voice signal is sampled in a telephone system CODEC;

(b) setting a magnitude of the charge pulse by providing the charge pulse to a current mirror having plural diversely sized transistors wherein a ratio of sizes of two of the plural transistors sets the magnitude of the charge pulse;

(c) setting a polarity of the charge pulse responsive to a sign bit signal in the voice signal; and

(d) providing the charge pulse with the set magnitude and polarity to the CODEC as an offset correction signal.

10. The method of claim 9 further comprising the step of selecting a further one of the plural transistors to be one of the two transistors to thereby selectably change the magnitude of the charge pulse.

11. A sign bit integrator for generating a signal for correcting an offset in a signal processing system comprising:

an input means for generating a charge pulse;

a current mirror connected to said input means for mirroring the charge pulse to an output means, said current mirror comprising,

plural transistors having different sizes wherein a ratio of the sizes defines a magnitude of the mirrored charge pulse;

a sign bit receptor connected to said current mirror for setting a polarity of the mirrored charge pulse responsive to a sign bit signal; and

said output means being connected to said current mirror for providing a signal for correcting an offset in the signal processing system.

12. The sign bit integrator of claim 11 wherein said plural transistors are MOS transistors.

13. The sign bit integrator of claim 11 wherein said plural transistors are in an integrated circuit and have active areas of the same length and unequal widths.

14. The sign bit integrator of claim 11 wherein the signal processing system is a telephone system CODEC and wherein said input means comprises an inverter for generating an output to a load capacitor for generating the charge pulse when a voice signal is sampled in the CODEC.

15. The sign bit integrator of claim 11 wherein said output means comprises an integrator capacitor for receiving the mirrored charge pulse as set by said sign bit receptor.

16. The sign bit integrator of claim 11 further comprising a second current mirror connected to said input means for mirroring the charge pulse to said output means, and wherein said sign bit receptor is connected to said second current mirror so that said current mirror and said second current mirror are for setting opposite polarities of the mirrored charge pulse responsive to the sign bit signal.

17. The sign bit integrator of claim 16 wherein said plural transistors are MOS transistors of a first conductivity type and wherein said second current mirror comprises plural MOS transistors of a second conductivity type.