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Physical address size selection and page size selection in an address translator

  • US 5,617,554 A
  • Filed: 12/23/1994
  • Issued: 04/01/1997
  • Est. Priority Date: 02/10/1992
  • Status: Expired due to Term
First Claim
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1. A processor generating linear addresses, said processor comprising:

  • a control unit having stored therein an indication in one of a plurality of states; and

    a paging unit coupled to said control unit to receive said indication, said paging unit translating said linear addresses into a physical address for accessing a physical address space, said paging unit simultaneously supporting paging using at least a first and a second page frame size while said indication is in a first of said plurality of states, said paging unit supporting paging using only one page frame size while said indication is in a second of said plurality of states.

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