Modular chip select control circuit and method for performing pipelined memory accesses

• US 5,617,559 A
• Filed: 08/31/1994
• Issued: 04/01/1997
• Est. Priority Date: 08/31/1994
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Eifert, James B., Le, Chinh H.
• Primary Examiner(s): Lane, Jack A.
• Assistant Examiner(s): Verbrugge, Kevin
• Application Number:
  US08/298,868
• Time in Patent Office: 944 Days
• Field of Search: 395/550, 395/800, 395/375, 395/496, 395/775, 395/494, 395/497.01, 365/230.06
• US Class Current: 711/169
• CPC Class Codes: G06F 12/1441 for a range
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4004 Coupling between buses
• CPC Class Codes: G06F 13/4018 with data-width conversion
• CPC Class Codes: G06F 13/4243 with synchronous protocol

Abstract

A modular chip select control circuit (80) is scalable by having an address decode stage (90) with a first number of address decoders, a control stage (100) with a second number of control units, and a pin configuration stage (110) with a third number of pin configuration logic circuits. These three numbers, defining the number of memory regions, the access pipeline depth, and the number of chip select signals, respectively, are independent and may be changed between chip designs to accommodate different system needs. The control stage includes an early pipeline control circuit (186) which allows the control units (170, 180) to pipeline pending memory cycles, based on an accessed region'"'"'s characteristics. The early pipeline control circuit (186) together with the control units (170, 180) enforce a set of pipelining rules to ensure data integrity and proper cycle termination, thus providing an efficient series of pipelined memory access cycles.

Claims

1. A modular chip select control circuit, comprising:

an address decode stage having a first plurality of address decoders, each address decoder associated with a programmable region and activating at least one corresponding control signal if an input address is within said programmable region;

a timing control stage coupled to said address decode stage, having a second plurality of control units, each control unit receiving said at least one corresponding control signal from each of said first plurality of address decoders and responsive thereto to provide a corresponding plurality of timing signals to control a memory access; and

a pin configuration stage coupled to said address decode stage and to said timing control stage, having a third plurality of pin configuration logic circuits, each pin configuration logic circuit programmable to provide a selected one of a plurality of chip select signals and responsive to selected ones of said corresponding plurality of timing signals of each of said second plurality of control units to provide said selected one of said plurality of chip select signals.

2. The modular chip select control circuit of claim 1, wherein said plurality of chip select signals comprises chip enable, write enable, and output enable.

3. The modular chip select control circuit of claim 1, wherein each of said first plurality of address decoders comprises:

a base address register for storing a base address of a corresponding programmable region;

an option register having bit fields for storing a region size and at least one attribute of said programmable region; and

a decoder having an input for receiving said input address and at least one input attribute signal, and an output for providing a match signal if, said input address is within said programmable region defined by said base address and said region size, and said at least one input attribute signal matches said at least one attribute of said programmable region.

4. The modular chip select control circuit of claim 1, wherein said timing control stage comprises:

a first control unit having a first input coupled to said address decode stage, a second input for receiving a first plurality of pipeline control signals, and an output coupled to said pin configuration stage for providing a first plurality of timing signals;

a second control unit having a first input coupled to said address decode stage, a second input for receiving a second plurality of pipeline control signals, and an output coupled to said pin configuration stage for providing a second plurality of timing signals; and

an early pipeline control circuit having an input coupled to said address decode stage, and first and second outputs respectively coupled to said second inputs of said first and second control units, said early pipeline control circuit providing said first and second pluralities of pipeline control signals according to a plurality of pipeline rules, thereby ensuring data integrity and proper cycle termination.

5. A method for performing pipelined memory accesses, comprising the steps of:

receiving and storing a first plurality of bits for controlling accesses to a first programmable region via a bus;

receiving and storing a second plurality of bits for controlling accesses to a second programmable region via said bus;

detecting a first access to said first programmable region using a portion of said first plurality of bits;

detecting a second access to said second programmable region using a portion of said second plurality of bits prior to a completion of said first access, said second access characterized as being a read access;

performing an address phase of said first access by providing a first chip select signal;

performing a data phase of said first access by providing a second chip select signal;

performing an address phase of said second access during at least a portion of said data phase of said first access by providing a third chip select signal; and

performing a data phase of said second access by providing a fourth chip select signal.

6. The method of claim 5, wherein said step of performing said address phase of said first access comprises the step of performing said address phase of said first access by providing a first chip enable signal, and wherein said step of performing said address phase of said second access comprises the step of performing said address phase of said second access by providing a second chip enable signal.

7. The method of claim 5, wherein said step of performing said data phase of said first access comprises the step of performing said data phase of said first access by providing either, a first output enable signal if said first access is a read cycle or a first write enable signal if said first access is a write cycle, and wherein said step of performing said data phase of said second access comprises the step of performing said data phase of said second access by providing a second output enable signal.

8. The method of claim 5, wherein said step of performing said address phase of said first access comprises the step of performing said address phase of said first access by providing a chip enable signal, and wherein said step of performing said address phase of said second access comprises the step of performing said address phase of said second access by providing said chip enable signal.

9. The method of claim 5, wherein said step of performing said data phase of said first access comprises the step of performing said data phase of said first access by providing either, an output enable signal if said first access is a read cycle or a write enable signal if said first access is a write cycle, and wherein said step of performing said data phase of said second access comprises the step of performing said data phase of said second access by providing said output enable signal.

10. The method of claim 5, further comprising the steps of:

receiving and storing bits for defining a plurality of regions associated with a corresponding plurality of programmable regions, including said first and second programmable regions;

detecting a third access to an unmapped address wherein said unmapped address is outside of all of said plurality of regions;

detecting a fourth access to an address within one of said plurality of regions prior to a completion of said third access;

performing an address phase of said fourth access by providing a fifth chip select signal, after a completion of said third access; and

performing a data phase of said fourth access by providing a sixth chip select signal.

11. The method of claim 5, further comprising the steps of:

receiving and storing a third plurality of bits for controlling accesses to a third programmable region;

receiving and storing a fourth plurality of bits for controlling accesses to a fourth programmable region;

detecting a third access to said third programmable region;

detecting a fourth access to said fourth programmable region prior to a completion of said third access;

performing an address phase of said third access by providing a fifth chip select signal;

performing a data phase of said third access by providing a sixth chip select signal;

performing an address phase of said fourth access by providing a seventh chip select signal, after a completion of said data phase of said third access if, at least one interface bit of said third plurality of bits and at least one interface bit of said fourth plurality of bits indicate that at least one of said third and fourth programmable regions is an asynchronous region, respectively; and

performing a data phase of said fourth access by providing an eighth chip select signal.

12. A method for performing pipelined memory accesses, comprising the steps of:

receiving and storing a first plurality of bits for controlling accesses to a first programmable region via a bus;

receiving and storing a second plurality of bits for controlling accesses to a second programmable region via said bus;

detecting a first write access to said first programmable region using a portion of said first plurality of bits;

detecting a second write access to said second programmable region using a portion of said second plurality of bits prior to a completion of said first write access;

performing an address phase of said first write access by providing a first chip select signal;

performing a data phase of said first write access by providing a second chip select signal;

performing an address phase of said second write access during at least a portion of said data phase of said first write access by providing a third chip select signal; and

performing a data phase of said second write access by providing a fourth chip select signal.

13. The method of claim 12, wherein said step of performing said address phase of said first write access comprises the step of performing said address phase of said first write access by providing a first chip enable signal, and wherein said step of performing said address phase of said second write access comprises the step of performing said address phase of said second write access by providing a second chip enable signal.

14. The method of claim 13, wherein said step of performing said data phase of said first write access comprises the step of performing said data phase of said first write access by providing a first write enable signal, and wherein said step of performing said data phase of said second write access comprises the step of performing said data phase of said second write access by providing a second write enable signal.

15. The method of claim 12, further comprising the steps of:

receiving and storing bits for defining a plurality of regions associated with a corresponding plurality of programmable regions, including said first and second programmable regions;

detecting a third access to an unmapped address wherein said unmapped address is outside of all of said plurality of regions;

detecting a fourth access to an address within one of said plurality of regions prior to a completion of said third access;

performing an address phase of said fourth access by providing a fifth chip select signal, after a completion of said third access; and

performing a data phase of said fourth access by providing a sixth chip select signal.

16. The method of claim 12, further comprising the steps of:

receiving and storing a third plurality of bits for controlling accesses to a third programmable region;

receiving and storing a fourth plurality of bits for controlling accesses to a fourth programmable region;

detecting a third access to said third programmable region;

detecting a fourth access to said fourth programmable region prior to a completion of said third access;

performing an address phase of said third access by providing a fifth chip select signal;

performing a data phase of said third access by providing a sixth chip select signal;

performing an address phase of said fourth access by providing a seventh chip select signal, after a completion of said data phase of said third access if, at least one interface bit of said third plurality of bits and at least one interface bit of said fourth plurality of bits indicate that at least one of said third and fourth programmable regions is an asynchronous region, respectively; and

performing a data phase of said fourth access by providing an eighth chip select signal.

17. A method for performing pipelined memory accesses, comprising the steps of:

receiving and storing a first plurality of bits for controlling accesses to a first programmable region via a bus;

receiving and storing a second plurality of bits for controlling accesses to a second programmable region Via said bus;

detecting a first access to said first programmable region using a portion of said first plurality of bits, said first access characterized as being a read access;

detecting a second access to said second programmable region using a portion of said second plurality of bits prior to a completion of said first access, said second access characterized as being a write access;

performing an address phase of said first access by providing a first chip select signal;

performing a data phase of said first access by providing a second chip select signal;

performing a first portion of an address phase of said second access by providing an address of said address phase of said second access during at least a portion of said data phase of said first access;

performing a second portion of said address phase of said second access after a completion of said data phase of said first access by providing a third chip select signal; and

performing a data phase of said second access by providing a fourth chip select signal.

18. The method of claim 17, wherein said step of performing said address phase of said first access comprises the step of performing said address phase of said first access by providing a first chip enable signal, and wherein said step of performing said address phase of said second access comprises the step of performing said address phase of said second access by providing a second chip enable signal.

19. The method of claim 17, further comprising the steps of:

receiving and storing bits for defining a plurality of regions associated with a corresponding plurality of programmable regions, including said first and second programmable regions;

detecting a third access to an unmapped address wherein said unmapped address is outside of all of said plurality of regions;

detecting a fourth access to an address within one of said plurality of regions prior to a completion of said third access;

performing an address phase of said fourth access by providing a fifth chip select signal, after a completion of said third access; and

performing a data phase of said fourth access by providing a sixth chip select signal.

20. The method of claim 17, further comprising the steps of:

receiving and storing a third plurality of bits for controlling accesses to a third programmable region;

receiving and storing a fourth plurality of bits for controlling accesses to a fourth programmable region;

detecting a third access to said third programmable region;

detecting a fourth access to said fourth programmable region prior to a completion of said third access;

performing an address phase of said third access by providing a fifth chip select signal;

performing a data phase of said third access by providing a sixth chip select signal;

performing an address phase of said fourth access by providing a seventh chip select signal, after a completion of said data phase of said third access if, at least one interface bit of said third plurality of bits and at least one interface bit of said fourth plurality of bits indicate that at least one of said third and fourth programmable regions is an asynchronous region, respectively; and

performing a data phase of said fourth access by providing an eighth chip select signal.

21. A method for performing pipelined memory accesses, comprising the steps of:

receiving and storing a first plurality of bits for controlling accesses to a first programmable region via a bus;

receiving and storing a second plurality of bits for controlling accesses to a second programmable region via said bus;

detecting a first access to said first programmable region using a portion of said first plurality of bits;

detecting a second access to said second programmable region using a portion of said second plurality of bits prior to a completion of said first access;

performing an address phase of said first access by providing a first chip select signal;

performing a data phase of said first access by providing a second chip select signal;

performing an address phase of said second access by providing a third chip select signal, during at least a portion of said data phase of said first access if, said first and second pluralities of bits indicate that at least one of said first and second programmable regions, respectively, provides a transfer acknowledge input signal to control a termination of a corresponding data phase, and said second plurality of bits indicates that said second programmable region can hold off a data output thereof; and

performing a data phase of said second access by providing a fourth chip select signal.

22. The method of claim 21, wherein said step of performing said address phase of said first access comprises the step of performing said address phase of said first access by providing a first chip enable signal, and wherein said step of performing said address phase of said second access comprises the step of performing said address phase of said second access by providing a second chip enable signal.

23. The method of claim 21, further comprising the steps of:

receiving and storing bits for defining a plurality of regions associated with a corresponding plurality of programmable regions, including said first and second programmable regions;

detecting a third access to an unmapped address wherein said unmapped address is outside of all of said plurality of regions;

detecting a fourth access to an address within one of said plurality of regions prior to a completion of said third access;

performing an address phase of said fourth access by providing a fifth chip select signal, after a completion of said third access; and

performing a data phase of said fourth access by providing a sixth chip select signal.

24. The method of claim 21, further comprising the steps of:

receiving and storing a third plurality of bits for controlling accesses to a third programmable region;

receiving and storing a fourth plurality of bits for controlling accesses to a fourth programmable region;

detecting a third access to said third programmable region;

detecting a fourth access to said fourth programmable region prior to a completion of said third access;

performing an address phase of said third access by providing a fifth chip select signal;

performing a data phase of said third access by providing a sixth chip select signal;

performing an address phase of said fourth access by providing a seventh chip select signal, after a completion of said data phase of said third access if, at least one interface bit of said third plurality of bits and at least one interface bit of said fourth plurality of bits indicate that at least one of said third and fourth programmable regions is an asynchronous region, respectively; and

performing a data phase of said fourth access by providing an eighth chip select signal.

25. A method for performing pipelined memory accesses, comprising the steps of:

receiving and storing a first plurality of bits for controlling accesses to a first programmable region via a bus;

receiving and storing a second plurality of bits for controlling accesses to a second programmable region via said bus;

detecting a first read access to said first programmable region using a portion of said first plurality of bits;

detecting a second read access to said second programmable region using a portion of said second plurality of bits prior to a completion of said first read access;

performing an address phase of said first read access by providing a first chip select signal;

performing a data phase of said first read access by providing a second chip select signal;

performing an address phase of said second read access by providing a third chip select signal, during at least a portion of said data phase of said first read access if, said first plurality of bits indicates that said first programmable region is a burstable region, and said second plurality of bits indicates that said second programmable region is a burstable region which can hold off a data output thereof; and

performing a data phase of said second read access by providing a fourth chip select signal.

26. The method of claim 25, wherein said step of performing said address phase of said first read access comprises the step of performing said address phase of said first read access by providing a first chip enable signal, and wherein said step of performing said address phase of said second read access comprises the step of performing said address phase of said second read access by providing a second chip enable signal.

27. The method of claim 26, further comprising the steps of:

receiving and storing bits for defining a plurality of regions associated with a corresponding plurality of programmable regions, including said first and second programmable regions;

detecting a third access to an unmapped address wherein said unmapped address is outside of all of said plurality of regions;

detecting a fourth access to an address within one of said plurality of regions prior to a completion of said third access;

performing an address phase of said fourth access by providing a fifth chip select signal, after a completion of said third access; and

performing a data phase of said fourth access by providing a sixth chip select signal.

28. The method of claim 26, further comprising the steps of:

receiving and storing a third plurality of bits for controlling accesses to a third programmable region;

receiving and storing a fourth plurality of bits for controlling accesses to a fourth programmable region;

detecting a third access to said third programmable region;

detecting a fourth access to said fourth programmable region prior to a completion of said third access;

performing an address phase of said third access by providing a fifth chip select signal;

performing a data phase of said third access by providing a sixth chip select signal;

performing an address phase of said fourth access by providing a seventh chip select signal, after a completion of said data phase of said third access if, at least one interface bit of said third plurality of bits and at least one interface bit of said fourth plurality of bits indicate that at least one of said third and fourth programmable regions is an asynchronous region, respectively; and

performing a data phase of said fourth access by providing an eighth chip select signal.