Method of forming a monolithic semiconductor integrated circuit having an N-channel JFET

• US 5,618,688 A
• Filed: 02/22/1994
• Issued: 04/08/1997
• Est. Priority Date: 02/22/1994
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Reuss, Robert H., Shapiro, Frederic B.
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): Pham, Long
• Application Number:
  US08/200,035
• Time in Patent Office: 1,141 Days
• Field of Search: 437/34, 437/56, 437/59, 437/31, 437/162, 437/192, 257/370, 257/378
• US Class Current: 438/189
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors

Abstract

An N-channel JFET (60) and a method of forming the N-channel JFET (60) in a BiCMOS process. The N-channel JFET (60) is monolithically fabricated with an N-channel IGFET (70), a P-channel IGFET (75), and an NPN BJT (80) in an epitaxial layer (21). The N-channel JFET (60) is formed in an isolated N-channel JFET region (24), the P-channel IGFET (75) is formed in an isolated P-channel IGFET region (27), and the NPN BJT (80) is formed in an isolated BJT region (29). The N-channel IGFET (70) is fabricated in a P-type well (26) that is not isolated from other N-channel IGFET'"'"'s in the epitaxial layer (21). Accordingly, the N-channel JFET (60), the N-channel IGFET (70), the P-channel IGFET (75), and an NPN BJT (80) are monolithically formed in the BiCMOS process.

Claims

1. A method of fabricating a monolithic semiconductor integrated circuit which comprises an N-channel junction field effect transistor, complementary insulated gate field effect transistors, and a bipolar junction transistor, the method comprising the steps of:

providing a semiconductor material of a first conductivity type and having a major surface;

forming an isolated N-channel junction field effect transistor region, an N-channel insulated gate field effect transistor region, an isolated P-channel insulated gate field effect transistor region, and an isolated bipolar junction transistor region in the semiconductor material, wherein the isolated N-channel junction field effect transistor region is contiguous with a buried layer of a second conductivity type;

forming a gate oxide layer on a portion of the major surface in the N-channel insulated gate field effect transistor region and on a portion of the major surface in the isolated P-channel insulated gate field effect transistor region;

forming a first gate conductor on the gate oxide on the portion of the major surface in the N-channel insulated gate field effect transistor region and a second gate conductor on the gate oxide on the portion of the major surface in the isolated P-channel insulated gate field effect transistor region;

forming a first source region and a first drain region in portions of the isolated N-channel junction field effect transistor region, a second source region and a second drain region in portions of the N-channel insulated gate field effect transistor region, and a collector contact region in a portion of the isolated bipolar junction transistor;

forming a third source region and a third drain region in portions of the isolated P-channel insulated gate field effect transistor region, and a gate contact region in a portion of the N-channel junction field effect transistor region;

forming a base region in another portion of the isolated bipolar junction transistor region;

forming a channel region in the N-channel junction field effect transistor region, wherein the channel region contains the first source region and the first drain region;

forming a polysilicon emitter in contact with a portion of the base region; and

forming a polysilicon gate, wherein the polysilicon gate is in contact with a portion of the channel region between the first source region and the first drain region.

2. The method of claim 1, wherein the steps of forming a polysilicon emitter and forming a polysilicon gate further comprise:

doping the polysilicon emitter with an impurity material of the second conductivity type; and

doping the polysilicon gate with an impurity material of the first conductivity type.

3. The method of claim 2, further including forming an active emitter region of the bipolar junction transistor by out-diffusing the impurity material from the polysilicon emitter into the base region.

4. The method of claim 2, further including forming an active gate region of the N-channel junction field effect transistor by out-diffusing the impurity material from the polysilicon gate into the channel region.

5. The method of claim 1, wherein the step of providing a semiconductor material comprises:

providing a semiconductor substrate of the first conductivity type having a principal surface;

forming at least one buried layer of the first conductivity type on the principal surface and at least one buried layer of the second conductivity type on the principal surface; and

forming an epitaxial layer on the principal surface, wherein the epitaxial layer has a thickness less than approximately two micrometers and includes the major surface.

6. The method of claim 1, further including forming a contact to the polysilicon emitter, a contact to the polysilicon gate, a contact to a portion of the isolated N-channel junction field effect transistor region adjacent to and spaced apart from the channel region, an isolation contact to a portion of an isolation region surrounding the N-channel junction field effect transistor region, a first source contact to the first source region, a first drain contact to the first drain region, a second source contact to the second source region, a second drain contact to the second drain region, a third source contact to the third source region, a third drain contact to the third drain region, a collector contact to a collector contact region, and a base contact to the base region, wherein the first source and drain contacts are for an N-channel junction field effect transistor, the second source and drain contacts are for an N-channel insulated gate field effect transistor, the third source and drain contacts are for a P-channel insulated gate field effect transistor, and the collector contact and the base contact are for a bipolar junction transistor, wherein the contact comprises a material selected from the group consisting of titanium silicide and platinum silicide.

7. The method of claim 1, wherein lateral boundaries of the isolated N-channel junction field effect transistor region are formed from lateral isolation means extending from the major surface to the buried layer, the lateral isolation means being contiguous with the major surface and the buried layer.

8. The method of claim 1 further including selecting a material for the gate conductor from the group consisting of metal and polysilicon.

9. A method of fabricating a monolithic semiconductor structure which comprises an N-channel junction field effect transistor, an N-channel insulated gate field effect transistor, a P-channel insulated gate field effect transistor, and a bipolar junction transistor, comprising the steps of:

providing a semiconductor material of P conductivity type having an epitaxial layer disposed thereon, the epitaxial layer having a major surface and at least three isolated regions extending from the major surface into the epitaxial layer and a P-type well extending from the major surface into the epitaxial layer, wherein a first isolated region serves as an N-channel junction field effect transistor active area, a second isolated region serves as a P-channel insulated gate field effect transistor active area, a third isolated region serves as a bipolar junction transistor active area, and the P-type well serves as an N-channel insulated gate field effect transistor active area, and wherein the first isolated region is of P conductivity type and is bounded by a dopant layer of N conductivity type;

forming a first insulated gate structure on a portion of the major surface in the second isolated region and forming a second insulated gate structure on a portion of the major surface of the P-type well;

forming a first source region and a first drain region in the first isolated region, a second source region and a second drain region in the P-type well, and a first doped region in the third isolated region, wherein the first and second source regions, the first and second drain regions, and the first doped region are of N conductivity type;

forming a third source region and a third drain region in the second isolated region, a second doped region in the third isolated region, a first doped region in the first isolated region, wherein the third source region, the third drain region, the second doped region in the third isolated region and the first doped region in the first isolated region are of P conductivity type;

forming a base region in the third isolated region, wherein the base region is of P conductivity type and encloses the second doped region;

forming a channel region in the first isolated region, wherein the channel region is of N conductivity type, and encloses the first source region and the first drain region;

forming an emitter in the second doped region of the third isolated region; and

forming a second doped region in the channel region, the second doped region between and spaced apart from the first source region and the first drain region, wherein the first and second doped regions serve as gates for the N-channel junction field effect transistor.

10. The method of claim 9 including forming the emitter as a doped polysilicon emitter, wherein a dopant of the doped polysilicon emitter out-diffuses into the second doped region in the third isolation region and the second doped region in the channel region comprises a polysilicon contact doped with a dopant that out-diffuses into the channel region.

11. The method of claim 10 further including forming the first doped region as an annular structure spaced apart from and laterally surrounding the channel region.

12. The method of claim 10, further including forming a silicide of one of platinum or titanium in a portion of the first source region, a portion of the first drain region, a portion of the second source region, a portion of the second drain region, a portion of the third source region, a portion of the third drain region, a portion of the a first doped region in the third isolation region, a portion of the a second doped region in the third isolation region, a portion of the doped polysilicon emitter, a portion of the first doped region in the first isolation region, and a portion of the second doped region in the channel region.

13. The method of claim 10, including implanting an impurity material of N conductivity type into a portion of the second doped region of the third isolation region to form an emitter;

doping a portion of the channel region with an impurity material of P conductivity type to form the second doped region, the portion of the channel region doped with the impurity material of P conductivity type being between and spaced apart from the first source region and the first drain region; and

wherein the step of forming a first doped region in the first isolation region comprises doping a portion of the first isolation region with an impurity material of P conductivity type to form the first doped region adjacent to and spaced apart from the channel region.