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Method of forming a monolithic semiconductor integrated circuit having an N-channel JFET

  • US 5,618,688 A
  • Filed: 02/22/1994
  • Issued: 04/08/1997
  • Est. Priority Date: 02/22/1994
  • Status: Expired due to Fees
First Claim
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1. A method of fabricating a monolithic semiconductor integrated circuit which comprises an N-channel junction field effect transistor, complementary insulated gate field effect transistors, and a bipolar junction transistor, the method comprising the steps of:

  • providing a semiconductor material of a first conductivity type and having a major surface;

    forming an isolated N-channel junction field effect transistor region, an N-channel insulated gate field effect transistor region, an isolated P-channel insulated gate field effect transistor region, and an isolated bipolar junction transistor region in the semiconductor material, wherein the isolated N-channel junction field effect transistor region is contiguous with a buried layer of a second conductivity type;

    forming a gate oxide layer on a portion of the major surface in the N-channel insulated gate field effect transistor region and on a portion of the major surface in the isolated P-channel insulated gate field effect transistor region;

    forming a first gate conductor on the gate oxide on the portion of the major surface in the N-channel insulated gate field effect transistor region and a second gate conductor on the gate oxide on the portion of the major surface in the isolated P-channel insulated gate field effect transistor region;

    forming a first source region and a first drain region in portions of the isolated N-channel junction field effect transistor region, a second source region and a second drain region in portions of the N-channel insulated gate field effect transistor region, and a collector contact region in a portion of the isolated bipolar junction transistor;

    forming a third source region and a third drain region in portions of the isolated P-channel insulated gate field effect transistor region, and a gate contact region in a portion of the N-channel junction field effect transistor region;

    forming a base region in another portion of the isolated bipolar junction transistor region;

    forming a channel region in the N-channel junction field effect transistor region, wherein the channel region contains the first source region and the first drain region;

    forming a polysilicon emitter in contact with a portion of the base region; and

    forming a polysilicon gate, wherein the polysilicon gate is in contact with a portion of the channel region between the first source region and the first drain region.

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