Method of making flash EPROM with conductive sidewall spacer contacting floating gate
First Claim
1. A method for fabricating a plurality of floating gate transistors on a substrate, comprising:
- forming a floating gate insulating layer over at least a portion of the substrate;
defining a plurality of strips of conductive material in a first layer of conductive material over the floating gate insulating layer;
exposing the substrate to dopants so that the plurality of strips act as a mask and a plurality of doped regions in the substrate are formed between the plurality of strips of conductive material;
annealing the substrate to drive in the dopants in the doped regions to establish buried diffusion regions aligned with the strips of conductive material;
forming a thicker insulator with an insulating material over the buried diffusion regions;
exposing the plurality of strips of conductive material;
depositing a second layer of conductive material over and in with the plurality of strips of conductive material;
etching the second layer of conductive material for a time to form self-aligned conductive spacer lines overlying the thicker insulator over the buried diffusion regions, each conductive spacer line contacting only one of the plurality of strips of conductive material;
forming a control gate insulator over the plurality of strips of conductive material and the conductive spacer lines;
depositing a third layer of conductive material over the control gate insulator; and
etching the third layer the conductive spacers, and the plurality of conductive strips to define control gate conductors and floating gates.
1 Assignment
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Accused Products
Abstract
Contactless flash EPROM cell and array designs, and methods for fabricating the same result in dense, segmentable flash EPROM chips. Also, an extended floating gate structure, and method for manufacturing the extended floating gate allow for higher capacitive coupling ratios in flash EPROM circuitry with very small design rules. The floating gates are extended in a symmetrical fashion in a drain-source-drain architecture, so that each pair of columns of cells has a floating gate which is extended in opposite directions from one another. This allows one to take advantage of the space on the cell normally consumed by the isolation regions, to extend the floating gates without increasing the layouts of the cells. Also, an easily scalable design is based on establishing conductive spacers on the sides of floating gate deposition layers which are used for self-alignment of the source and drain. According to this structure, a floating gate deposition is first laid down and used for establishing self-aligned source and drain diffusion regions. After deposition of the source and drain, conductive spacers are deposited on the sides of the first floating gate structure. These conductive spacers can be deposited in a symmetrical fashion, and are easily scalable to large scale arrays of flash EPROM designs.
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Citations
10 Claims
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1. A method for fabricating a plurality of floating gate transistors on a substrate, comprising:
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forming a floating gate insulating layer over at least a portion of the substrate; defining a plurality of strips of conductive material in a first layer of conductive material over the floating gate insulating layer; exposing the substrate to dopants so that the plurality of strips act as a mask and a plurality of doped regions in the substrate are formed between the plurality of strips of conductive material; annealing the substrate to drive in the dopants in the doped regions to establish buried diffusion regions aligned with the strips of conductive material; forming a thicker insulator with an insulating material over the buried diffusion regions; exposing the plurality of strips of conductive material; depositing a second layer of conductive material over and in with the plurality of strips of conductive material; etching the second layer of conductive material for a time to form self-aligned conductive spacer lines overlying the thicker insulator over the buried diffusion regions, each conductive spacer line contacting only one of the plurality of strips of conductive material; forming a control gate insulator over the plurality of strips of conductive material and the conductive spacer lines; depositing a third layer of conductive material over the control gate insulator; and etching the third layer the conductive spacers, and the plurality of conductive strips to define control gate conductors and floating gates. - View Dependent Claims (2, 3, 4)
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5. A method for fabricating a plurality of flash EPROM transistors on a substrate, comprising:
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forming a floating gate insulating layer over at least a portion of the substrate; defining a plurality of strips of polysilicon in a first polysilicon layer over the floating gate insulating layer; exposing the substrate to dopants so that the plurality of strips act as a mask and a plurality of doped regions in the substrate are formed between the plurality of strips of conductive material; annealing the substrate to drive in the dopants in the doped regions to establish buried diffusion regions aligned with the strips of polysilicon; forming a thicker insulator with an insulating material over the buried diffusion regions; exposing the plurality of strips of polysilicon; depositing a second polysilicon layer over and in contact with the plurality of strips; etching the second polysilicon layer for a time to form self-aligned conductive spacer lines overlying the thicker insulator over the buried diffusion regions, each conductive spacer line contacting only one of the plurality of strips; forming a control gate insulator over the plurality of strips and the conductive spacer lines; depositing a third polysilicon layer over the control gate insulator; and etching the third layer the conductive spacers, and the plurality of conductive strips to define control gate conductors and floating gates. - View Dependent Claims (6, 7, 8, 9, 10)
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Specification