Layered solid state photodiode sensor array

• US 5,619,033 A
• Filed: 06/07/1995
• Issued: 04/08/1997
• Est. Priority Date: 06/07/1995
• Status: Expired due to Term

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: Weisfield, Richard L.
• Primary Examiner(s): LE, QUE TAN
• Application Number:
  US08/483,406
• Time in Patent Office: 671 Days
• Field of Search: 250/208.1, 250/214.1, 257/458, 257/444, 257/446, 257/448, 257/53, 257/292
• US Class Current: 250/208.1
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers

Abstract

A photodetecting device and a method for constructing the photodetecting device. The photodetecting device provides at least one transistor formed over a substrate and at least one photodiode formed over the at least one transistor. Each of the at least one photodiode is coupled to one of the at least one transistor. The fill factor of the photodiode is very high even when the resolution of the photodetecting device is increased. The photodetecting devices are formed in a matrix having rows and columns. The matrix of photodetecting devices forms a two dimensional imaging device.

Claims

1. A photodetecting device, comprising:

a substrate;

at least one transistor formed over the substrate; and

at least one photodiode formed over the at least one transistor, wherein each of the at least one photodiode is coupled to one of the at least one transistor, and the coupling comprises an electrical connection between the photodiode and a drain electrode of the transistor.

2. The device of claim 1, wherein a first passivation layer is formed between the at least one transistor and the at least one photodiode, each of the at least one photodiode comprising:

an n+ layer formed over the first passivation layer;

an amorphous silicon layer formed over the n+ layer;

a p+ layer formed over the amorphous silicon layer; and

a conductive layer formed over the p+ layer.

3. The device of claim 2, wherein:

the n+ layer is about 500 angstroms to about 1000 angstroms thick;

the amorphous silicon layer is about 0.5 microns to about 2.0 microns thick;

the p+ layer is about 100 angstroms thick; and

the conductive layer is about 500 angstroms to about 1000 angstroms thick.

4. The device of claim 2, each of the at least one photodiode further comprising a bias contact formed over the conductive layer, wherein the bias contact shields one of the at least one transistor from light.

5. The device of claim 2, wherein the at least one photodiode is arranged in a matrix having at least one row and at least one column, each of the at least one photodiode being separated from adjacent photodiodes by a notch.

6. The device of claim 5, wherein the notch is about 3 microns to about 10 microns wide.

7. The device of claim 5, wherein the notch is formed in the n+ layer.

8. The device of claim 5, wherein a metal layer is formed between the n+ layer and the first passivation layer, the notch being formed in the metal layer and the n+ layer.

9. The device of claim 5, wherein the notch is formed in the conductive layer, the p+ layer, the amorphous silicon layer and the n+ layer.

10. The device of claim 5, wherein a metal layer is formed between the n+ layer and the first passivation layer, the notch being formed in the conductive layer, the p+ layer, the amorphous silicon layer, the n+ layer, and the metal layer.

11. The device of claim 2, further comprising:

at least one via hole formed in the first passivation layer, each of the at least one via hole exposing a drain electrode of one of the at least one transistor, the n+ layer contacting the drain electrode of the at least one transistor through each of the at least one via hole forming at least one back contact.

12. The device of claim 11, wherein each of the at least one back contact is about 10 microns wide.

13. The device of claim 2, further comprising:

at least one via hole formed in the first passivation layer, each of the at least one via hole exposing a drain electrode of one of the at least one transistor; and

a metal layer formed between the n+ layer and the first passivation layer, the metal layer contacting the drain electrode of the at least one transistor through each of the at least one via hole forming at least one back contact.

14. The device of claim 13, wherein the at least one back contact is about 10 microns wide.

15. A method for manufacturing a photodetecting device, comprising:

forming at least one transistor over a substrate; and

forming at least one photodiode over the at least one transistor, each of the at least one photodiode being coupled to one of the at least one transistor, the coupling comprising an electrical connection between the photodiode and a drain electrode of the transistor.

16. The method of claim 15, further comprising:

forming a first passivation layer over the at least one transistor formed over the substrate;

forming an n+ layer over the passivation layer;

forming an amorphous silicon layer over the n+ layer;

forming a p+ layer over the amorphous silicon layer; and

forming a conductive layer over the p+ layer.

17. The method of claim 16, wherein the at least one photodiode is arranged in a matrix having at least one row and at least one column, each of the at least one photodiode being separated from adjacent photodiodes by a notch.

18. The method of claim 17, wherein the notch is formed by;

masking the n+ layer; and

etching the n+ layer.

19. The method of claim 17, further comprising forming a metal layer between the n+ layer and the first passivation layer, wherein the notch is formed by;

masking the n+ layer; and

etching through the n+ layer and the metal layer.

20. The method of claim 16, further comprising:

masking the first passivation layer;

etching the first passivation layer to form at least one via hole exposing a drain electrode of each of the at least one transistor; and

forming the n+ layer over the first passivation layer, the n+ layer contacting the drain electrode of each of the at least one transistor through the at least one via hole forming at least one back contact.

21. The method of claim 16, further comprising:

masking the first passivation layer;

etching the first passivation layer to form at least one via hole exposing a drain electrode of each one of the at least one transistor; and

forming a metal layer between the first passivation layer and the n+ layer, the metal layer contacting the drain electrode of each of the at least one transistor through the at least one via hole forming at least one back contact.