Memory for an electronic token

• US 5,619,066 A
• Filed: 08/31/1994
• Issued: 04/08/1997
• Est. Priority Date: 05/15/1990
• Status: Expired due to Term

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Payne, William L. II, Lehmann, Guenther H., Lee, Robert D., Zanders, Gary V., Kurkowski, Hal, Curry, Stephen M., Deierling, Kevin E., Bolan, Michael L., Dias, Donald R.
• Primary Examiner(s): LANE, JOHN A
• Application Number:
  US08/299,040
• Time in Patent Office: 951 Days
• Field of Search: 395/400, 395/425, 364/270.05, 364/270.07, 364/271.05, 364/950.01, 364/950.04, 364/DIG. 1, 364/DIG. 2, 364/200 MS File, 364/900 MS File, 235/441, 235/492, 257/678, 257/679, 257/684, 257/730, 257/731, 257/732, 375/7, 365/189.06, 365/194, 365/221
• US Class Current: 257/679
• CPC Class Codes: G01K 1/028 arrangements for numerical indication
• CPC Class Codes: G01K 3/10 in respect of time, e.g. reacting only to a quick change of temperature
• CPC Class Codes: G01K 7/245 in an oscillator circuit
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 3/0383 Signal control means within the pointing device
• CPC Class Codes: G06F 3/04897 Special input arrangements or commands for improving display capability
• CPC Class Codes: G06K 19/07 with integrated circuit chips
• CPC Class Codes: G06K 7/0021 for reading/sensing record carriers having surface contacts
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: G11C 8/20 Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access
• CPC Class Codes: H01L 23/58 Structural electrical arrangements for semiconductor devices not otherwise provided for , e.g. in combination with batteries H01L23/49593, H01L23/49596 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A serial-port memory is positioned in a substantially token-shaped body. The substantially token-shaped body has a perimeter and a flange extending from a portion of the perimeter. The serial-port memory comprises a serial port, a scratchpad memory coupled to the serial port, a second memory coupled to the scratchpad memory; and control logic coupled to the serial port and the scratchpad and second memories. The control logic transfers information from the scratchpad memory to the second memory as a block pursuant to a block transfer command received at the serial port. The electronic token has a first electrically conductive surface and a second electrically conductive surface that combines to create a hollow cavity and the serial port, scratchpad memory, second memory, and control logic positioned inside the hollow cavity, the first conductive surface and the second conductive surface can be electrically coupled to transmit electrical signals generated by the serial port, scratchpad memory, second memory, and control logic and to receive externally generated electrical signals. The first electrically conductive surface and the second electrically conductive surface are preferably planar. The control logic includes a cyclic redundancy check generator. Third and fourth memories can be coupled to the scratchpad memory, wherein the control logic transfers information as a block from the scratchpad memory to one of the second, third, and fourth memories pursuant to a block transfer command received at the serial port.

Claims

1. A serial-port memory positioned in a substantially token-shaped body, said substantially token-shaped body having a perimeter and a flange extending from a portion of said perimeter, said substantially token-shaped body comprising a plurality of electrically conductive surfaces physically insulated from one another, said plurality of electrically conductive surfaces forming said substantially token-shaped body and one electrically conductive surface of said plurality of electrically conductive surfaces forming said flange, said flange residing approximately in one geometric plane comprising:

(a) a serial port electrically coupled to said plurality of electrically conductive surfaces;

(b) a scratchpad memory electrically coupled to said serial port;

(c) a second memory electrically coupled to said scratchpad memory; and

(d) control logic electrically coupled to said serial port, said scratchpad memory and said second memory, said control logic transfering information from said scratchpad memory to said second memory as a block pursuant to a block transfer command received at said serial port via said plurality of electrically conductive surfaces,

wherein said plurality of electrically conductive surfaces of said substantially token-shaped body comprise a first electrically conductive surface and a second electrically conductive surface that combine to create a hollow cavity, said serial port, scratchpad memory, second memory, and control logic positioned inside said hollow cavity, said first electrically conductive surface and said second electrically conductive surface electrically coupled to said serial port to transmit electrical signals generated by said serial port, scratchpad memory, second memory, and control logic and to receive externally generated electrical signals; and

wherein said first electrically conductive surface and said second electrically conductive surface are planar surfaces, and further wherein a portion of said first electrically conductive surface and said second electrically conductive surface are parallel to one another.

2. The memory of claim 1, wherein:

(a) said control logic only transfers information to said second memory after a password identifying said second memory has been received at said serial port.

3. The memory of claim 1, wherein:

(a) said control logic is electrically coupled to cyclic redundancy check circuitry that compares a portion of said information to a stored cyclic redundancy check value, said cyclic redundancy check circuitry also positioned in said substantially token-shaped body.

4. The memory of claim 3, wherein said cyclic redundancy check circuitry is comprised of a cyclic redundancy check generator that receives said stored cyclic redundancy check value and compares it to a first value generated by using a serial number stored in said second memory.

5. The memory of claim 4, wherein said first value is generated from said serial number using a generating polynomial x³ +x² +1.

6. The memory of claim 4, wherein said serial number is 48 bits, said cyclic redundancy check is one byte.

7. The memory of claim 3, wherein a serial number and said cyclic redundancy check value is embedded in said control logic, a cyclic redundancy check generator evaluates said serial number, said cyclic redundancy check generator inserts said serial number into a preselected algorithm that generates an output which is compared to said cyclic redundancy check value.

8. The memory of claim 1, further comprising:

(a) third and fourth memories coupled to said scratchpad memory, said third and fourth memories positioned in said substantially token-shaped body; and

(b) wherein said control logic transfers information as a block from said scratchpad memory to one of said second, third, and fourth memories pursuant to a block transfer command received at said serial port.

9. The memory of claim 1, wherein said serial port, said scratchpad memory, said second memory and said control logic are powered by a battery.

10. The memory of claim 9, further comprising:

(f) a voltage level detector coupled to said first and second electrically conductive surfaces for receiving signals applied as voltage level differences between said first and second electrically conductive surfaces; and

(g) a switch connecting said first and second electrically conductive surfaces for sending signals by changing a resistance between said first and second electrically conductive surfaces.

11. The memory of claim 10, wherein said voltage level differences are approximately 5 volts and said voltage level differences correspond to a logical high and a logical low.

12. The memory of claim 9, wherein said serial port, said scratchpad memory, said second memory and said control logic are integrated on a monolithic piece of silicon.

13. The memory of claim 9, wherein said battery is a low voltage battery having a charge of approximately 1.5 volts.

14. The memory of claim 9, wherein said scratchpad memory has a first size and said second memory has a second size.

15. The memory of claim 14, wherein said second memory is static random access memory.

16. The memory of claim 14, wherein said second size is less than or equal to 4K bytes.

17. The memory of claim 1, wherein said serial port, said scratchpad memory, said second memory and said control logic are powered by voltage intermittently applied between said first and second electrically conductive surfaces.

18. The memory of claim 17, further comprising a capacitor for storing energy from said voltage intermittently applied between said first and second electrically conductive surfaces.

19. The memory of claim 1, wherein:

(a) said first electrically conductive surface comprises a first flat face; and

(b) said second electrically conductive surface comprises

(b1) a second flat face parallel to said first flat face; and

(b2) a portion of a first electrically conductive surface which is approximately perpendicular to said first flat face and said second flat face.

20. The memory of claim 1, wherein said substantially token-shaped body is button-shaped.

21. The memory of claim 1, wherein said substantially token-shaped body is mountable to a physical item.

22. The memory of claim 1, wherein said substantially token-shaped body is mountable to a physical item, said physical item is selected from a group consisting of maintenance records, retail products, machinery, cards, personnel identification badges, and any combination thereof.

23. The memory of claim 1, wherein said substantially token-shaped body has only said first and second electrically conductive surface.

24. The memory of claim 1, wherein said serial port, said scratchpad memory, said second memory and said control logic are packaged in a low-height package.

25. The memory of claim 24, wherein said low-height package is selected from the group consisting of a flat pack and small out-line integrated circuit, and any combination thereof.

26. The memory of claim 1, wherein said serial port, said scratchpad memory, said second memory and said control logic is combined into an integrated circuit that is mounted on a very small printed circuit board positioned in said substantially token-shaped body.

27. The memory of claim 1, wherein said substantially token-shaped body is cylindrical in shape and has a diameter approximately equal to 16 mm.

28. The memory of claim 1, wherein said substantially token-shaped body is comprised of metal.

29. The memory of claim 1, wherein a bus master module controls communication to and from said serial port.

30. The memory of claim 29, wherein said bus master module holds a data line to a first voltage level for a first time period, creates a transition between said first voltage level and a second voltage level, holds the data line at said second voltage for a second time period;

and samples said voltage level of said data line to determine whether said data value is a first data value or a second data value at a first sample time.

31. The memory of claim 30, wherein said first time period is at least one microsecond.

32. The memory of claim 30, wherein said first voltage is approximately five volts and corresponds to a logic high level.

33. The memory of claim 30, wherein said second voltage is approximately ground and corresponds to a logic low level.

34. The memory of claim 30, wherein said transition provides a coordinating time from which said memory coordinates internal operations.

35. The memory of claim 30, wherein said second time period is at least one microsecond.

36. The memory of claim 30, wherein said first sample time is at least 30 microseconds from said transition.

37. The memory of claim 30, wherein said bus master module holds a data line coupled to said serial port via a first electrically conductive surface to a first voltage level for a first time period, creates a transition between said first voltage level and a second voltage level, holds said first data line to said second voltage for a second time period, and samples said voltage level of said data line by said bus master module to determine whether said data value is a first data value or a second data value at a first time.

38. The memory of claim 37, wherein said first time period is at least one microsecond.

39. The memory of claim 37, wherein said first time is approximately 10 microseconds after said transition.

40. The memory of claim 37, wherein said transition is a falling edge.

41. The memory of claim 37, wherein said first voltage is approximately five volts and corresponds to a logic high level.

42. The memory of claim 37, wherein said second voltage is approximately ground and corresponds to a logic low level.

43. The memory of claim 37, wherein said transition provides a coordinating time from which said slave module coordinates internal operations.

44. The memory of claim 37, wherein said second voltage level is 5 volts and corresponds to a logic high level.

45. The memory of claim 37, wherein said first time period and said second time period when combined together do not exceed 60 microseconds from said transition.

46. The memory of claim 37, wherein said first data value and said second data values are selected from the group consisting of a logical one value and a logical zero value.

47. The memory of claim 37, wherein said first time period and said second time period when combined together create a fourth time period which is approximately four times a difference between said first time period and said transition.

48. The memory of claim 1, wherein said serial port comprises a first input and a ground input coupled to said plurality of electrically conductive surfaces.

49. The memory of claim 1, wherein said serial port comprises only a first input coupled to said first electrically conductive surface and a ground input coupled to said second electrically conductive surface.

50. The memory of claim 1, wherein said control logic transfers information from said second memory to said serial port as a block pursuant to a second block transfer command received at said serial port.

51. The memory of claim 50, wherein said second block transfer command is a read command.

52. The memory of claim 1, wherein said block command is a write command.