Method and circuitry for drag braking a polyphase DC motor

• US 5,619,109 A
• Filed: 06/07/1995
• Issued: 04/08/1997
• Est. Priority Date: 07/01/1993
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: Schlager, Karl M., Cameron, Scott W.
• Primary Examiner(s): Ro, Bentsu
• Application Number:
  US08/477,458
• Time in Patent Office: 671 Days
• Field of Search: 318/138, 318/254, 318/375, 318/376, 318/379, 318/439, 369/189, 369/239, 369/264, 369/266, 369/268
• US Class Current: 318/375
• CPC Class Codes: H02P 6/24 Arrangements for stopping

Abstract

A method and circuit for braking a forward rotation of a rotor of a polyphase DC motor. A commutation sequencer is incremented by several phases to produce an incremented commutation sequence to produce a magnetic flux vector that lags a magnetic pole of the motor. Driving currents are applied to coils of the motor in accordance with the incremented commutation sequence to brake the rotor. The method is implemented in a circuit that has a sequencer for incrementally generating sets of commutation signals to select stator coils for energization to rotate the rotor. A power stage to which the commutation signals are applied energizes the selected coils in accordance with the commutation signals. A circuit interrupts the energization of the selected coils and the commutation sequence is altered to produce a sequence that produces a negative torque on the rotor. Circuits are also provided to inhibit application of the altered commutation sequence until recirculation currents in the power stage caused by the coils in response to the reduction of the input voltage have fallen below a predetermined level, and to inhibit application of the altered commutation sequence until a voltage on a sense resistor between the power stage and a reference potential has fallen below a predetermined level after an operation of the circuit for interrupting the energization of the selected coils.

Claims

1. A data storage system, comprising:

a polyphase DC motor for rotating a data medium, having a rotor and a plurality of stator coils;

a sequencer for incrementally generating sets of commutation signals to select stator coils for energization to rotate said rotor according to a commutation sequence that increments in a forward direction and generates a flux vector that leads the rotor;

a power stage to which said commutation signals are applied to energize the selected coils in accordance with said commutation signals;

a circuit for interrupting the energization of the selected coil;

a circuit for producing an altered commutation sequence that increments in a forward direction and generates a flux vector that lags the rotor; and

a circuit for applying the altered commutation sequence to said power stage to brake the rotation of the rotor.

2. The system of claim 1 further comprising a circuit for removing an input voltage from the power stage in response to a signal to brake the rotor, and for reapplying the input voltage after the altered commutation sequence has been applied.

3. The system of claim 2 further comprising:

a circuit for inhibiting application of said altered commutation sequence until recirculation currents in said power stage caused by the coils in response to the reduction of the input voltage have fallen below a predetermined level.

4. The system of claim 2 further comprising:

a circuit for inhibiting application of said altered commutation sequence until a voltage on a sense resistor between the power stage and a reference potential has fallen below a predetermined level after an operation of the circuit for interrupting the energization of the selected coils.

5. The system of claim 2 further comprising:

a circuit for inhibiting application of said altered commutation sequence until recirculation currents in said power stage caused by the coils in response to the reduction of the input voltage have fallen below a predetermined level; and

a circuit for inhibiting application of said altered commutation sequence until a voltage on a sense resistor between the power stage and a reference potential has fallen below a predetermined level after an operation of the circuit for interrupting the energization of the selected coils.

6. The system of claim 1 wherein said circuit for producing an altered commutation sequence comprises a plurality of multiplexers connected to output the sets of commutation signals in a first order in the absence of a reverse torque signal, and to output the sets of commutation signals in a second order in the presence of a reverse torque signal.

7. The system of claim 1 wherein said altered commutation sequence is 180°

out of phase from an original commutation sequence.

8. The system of claim 1 further comprising circuitry for incrementing said sequencer in response to a back emf signal from at least one of said stator coils.

9. A data storage system, comprising:

a polyphase DC motor for rotating a data medium, having a rotor and a plurality of stator coils;

a power stage to energize selected ones of the plurality of stator coils;

a sequencer for incrementally generating sets of commutation signals for application to said power stage to select stator coils for energization to rotate said rotor in a forward direction according to a commutation sequence;

said commutation signals being selected to create a magnetic flux vector that moves in advance of a pole of said rotor to cause said rotor to rotate in a forward direction;

a circuit for interrupting the energization of the stator coils;

a circuit for altering the commutation sequence to produce an altered commutation sequence in the forward direction that creates a flux vector that moves behind the pole of the rotor to apply a negative torque to the rotor; and

a circuit to adjust a supply voltage to the power stage to control a magnitude of the negative torque applied to the rotor.

10. The system of claim 9 wherein said altered commutation sequence is 180°

out of phase from an original commutation sequence.

11. The system of claim 9 further comprising circuitry for incrementing said sequencer in response to a back emf signal from at least one of said stator coils.

12. A data storage system, comprising:

a polyphase DC motor for rotating a data medium, having a rotor and a plurality of stator coils;

a power stage to energize selected ones of the plurality of stator coils;

a sequencer for incrementally generating sets of commutation signals for application to said power stage to select stator coils for energization to rotate said rotor according to a commutation sequence;

said commutation signals being selected to create a magnetic flux vector that moves in advance of a pole of said rotor to cause said rotor to rotate in a forward direction;

a circuit for interrupting the energization of the stator coils;

a circuit for altering the commutation sequence to produce an altered commutation sequence that creates a flux vector that moves behind the pole of the rotor to apply a negative torque to the rotor; and

a circuit for reducing an input voltage from the power stage in response to a signal to brake the rotor, and for reapplying the input voltage after the altered commutation sequence has been applied.

13. The system of claim 12 further comprising a circuit to inhibit application of said altered commutation sequence until recirculation currents in said power stage caused by the coils in response to the reduction of the input voltage have fallen below a predetermined level.

14. The system of claim 12 further comprising a circuit to inhibit application of said altered commutation sequence until a voltage on a sense resistor between the power stage and a reference potential has fallen below a predetermined level after an operation of the circuit for interrupting the energization of the stator coils.

15. The system of claim 12 further comprising a circuit to inhibit application of said altered commutation sequence until recirculation currents in said power stage caused by the coils in response to the reduction of the input voltage have fallen below a predetermined level, and further comprising a circuit to inhibit application of said altered commutation sequence until a voltage on a sense resistor between the power stage and a reference potential has fallen below a predetermined level after an operation of the circuit for interrupting the energization of the stator coils.

16. A data storage system comprising:

a polyphase DC motor for rotating a data medium, having a rotor and a plurality of stator coils;

a power stage to energize selected ones of the plurality of stator coils;

a sequencer for incrementally generating sets of commutation signals for application to said power stage to select stator coils for energization to rotate said rotor according to a commutation sequence;

said commutation signals being selected to create a magnetic flux vector that moves in advance of a pole of said rotor to cause said rotor to rotate in a forward direction;

a circuit for interrupting the energization of the stator coils; and

a circuit for altering the commutation sequence to produce an altered commutation sequence that creates a flux vector that moves behind the pole of the rotor to apply a negative torque to the rotor,

wherein said circuit for altering the commutation sequence to produce an altered commutation sequence comprises a plurality of multiplexers connected to output the sets of commutation signals in a first order in the absence of a reverse torque signal, and to output the sets of commutation signals in a second order in the presence of a reverse torque signal.

17. A data storage system comprising:

a brushless and sensorless DC motor for rotating a data medium, having a rotor and having a stator with at least three coils;

energizing means for energizing said at least three coils in accordance with sequential commutation sequences;

interrupting means for interrupting the energizing of said at least three coils;

monitoring means for monitoring the voltage outputs of said at least three coils after the interrupting means has interrupted the energizing of said at least three coils; and

altering means for producing an altered commutation sequence that produces a negative torque on the rotor.

18. The system of claim 17 wherein said energizing means comprises a transconductance circuit.

19. The system of claim 17 further comprising a sequencer for generating the sequential commutation sequence.

20. The system of claim 19 further comprising a multiplexer that is controlled by a brake signal, and wherein the sequencer has six output signals that are connected to the multiplexer, said multiplexer having six outputs that are connected to the energizing means, said multiplexer being connected to output the sets of commutation signals in a first order in the absence of a brake signal, and to output the sets of commutation signals in a second order in the presence of a brake signal.

21. The system of claim 19, further comprising a multiplexer that is controlled by a brake signal output of the altering means;

wherein the sequencer has six output signals that are connected to the multiplexer, said multiplexer having six outputs that are connected to the energizing means, said multiplexer being connected to output the sets of commutation signals in a first order in the absence of a brake signal, and to output the sets of commutation signals in a second order in the presence of a brake signal;

and wherein the multiplexer comprises;

a first transmission gate with an input connected to a sixth output of the sequencer;

a second transmission gate with an input connected to a third output of the sequencer and an output connected to an output of said first transmission gate;

a third transmission gate with an input connected to a first output of the sequencer;

a fourth transmission gate with an input connected to a fourth output of the sequencer and an output connected to an output of said third transmission gate;

a fifth transmission gate with an input connected to the second output of the sequencer;

a sixth transmission gate with an input connected to a fifth output of the sequencer and an output connected to an output of said fifth transmission gate;

a seventh transmission gate with an input connected to the third output of the sequencer;

an eighth transmission gate with an input connected to the sixth output of the sequencer and an output connected to an output of said seventh transmission gate;

a ninth transmission gate with an input connected to the fourth output of the sequencer;

a tenth transmission gate with an input connected to the first output of the sequencer and an output connected to an output of said ninth transmission gate;

an eleventh transmission gate with an input connected to the fifth output of the sequencer;

a twelfth transmission gate with an input connected to the second output of the sequencer and an output connected to an output of said eleventh transmission gate;

an inverter connected to receive the brake signal output, for outputting a signal to a control input of said second transmission gate, a control input of said fourth transmission gate, a control input of said sixth transmission gate, a control input of said eighth transmission gate, a control input of said tenth transmission gate, a control input of said twelfth transmission gate, a complement control input of said first transmission gate, a complement control input of said third transmission gate, a complement control input of said fifth transmission gate, a complement control input of said seventh transmission gate, a complement control input of said ninth transmission gate, and a complement control input of said eleventh transmission gate;

said brake signal output being connected to a complement control input of said second transmission gate, to a complement control input of said fourth transmission gate, to a complement control input of said sixth transmission gate, to a complement control input of said eighth transmission gate, to a complement control input of said tenth transmission gate, to a complement control input of said twelfth transmission gate, to a control input of said first transmission gate, to a control input of said third transmission gate, to a control input of said fifth transmission gate, to a control input of said seventh transmission gate, to a control input of said ninth transmission gate, and to a control input of said eleventh transmission gate.

22. The system of claim 17 wherein said altered commutation sequence is 180°

out of phase from an original commutation sequence.