Analog-to-digital converter with optional low-power mode
First Claim
1. An IC chip having A/D converter circuitry for converting an applied analog signal to a corresponding digital signal;
- said chip including one pin to which a conversion start signal (CONVST) can be applied from associated apparatus;
means to transmit an end-of-conversion signal (EOC);
said A/D circuitry including first terminal means to receive a convert-enable signal (CONVEN) for initiating a conversion and second terminal means to transmit a mode switchover signal (SLEEP) to place the A/D circuitry either in a normal-power mode or in a low-power mode in which the power consumed between conversions is substantially less than that consumed during a conversion operation;
control circuitry for developing said CONVEN signal and said mode switchover signal, comprising;
a first D-type flip-flop with reset;
means applying a fixed signal to the D-terminal of said first D-type flip-flop;
means connecting said CONVST signal to the clock input of said first D-type flip-flop;
means connecting said EOC signal to the reset (R) terminal of said first D-type flip-flop;
means connecting the Q output of said first D-type flip-flop to said first terminal means to initiate an analog-to-digital conversion in response to an output signal of said first D-type flip-flop;
a second D-type flip-flop with set;
means connecting the clock input of said second D-type flip-flop to the output of said first D-type flip-flop;
means connecting said CONVST signal to the D input of said second D-type flip-flop;
means connecting the complement of said CONVST signal to the set (S) terminal of said second D-type flip-flop; and
means connecting the Q output of said second D-type flip-flop to said second terminal means to provide for low-power operation upon receipt of said Q output from said second D-type flip-flop.
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Accused Products
Abstract
An IC chip having an analog-to-digital converter together with control circuitry for effecting switchover between normal-power mode and low-power mode. The control circuitry includes a first D-type flip-flop with reset which receives on its "D" input a continuous high signal; on its differential clock inputs the flip-flop receives complementary logic signals derived from the "conversion start" (CONVST) signal applied to one pin of an 8-pin chip. In normal mode, the CONVST signal is a short pulse having an initial negative-going (falling) leading edge, and the flip-flop responds to that leading edge by producing a high Q output (CONVEN). This signals the A/D converter to carry out a conversion. In low-power mode, the CONVST short pulse is positive. The subsequent negative-going (falling) trailing edge of the pulse activates the flip-flop to cause its Q output to go high and turn on the A/D converter. The control circuitry includes a second D-type flip-flop (this one with set) which receives on its D input the CONVST signal. The Q output. of the second flip-flop generates a mode switchover control signal (designated SLEEPB). During low-power mode, established by the use of positive-going CONVST pulses, the low CONVEN signal at the end of conversion clocks the second flip-flop to sample CONVST on its D input, thereby causing the Q output of the second flip-flop (SLEEPB) to go low and switch the A/D converter into low-power status.
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Citations
9 Claims
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1. An IC chip having A/D converter circuitry for converting an applied analog signal to a corresponding digital signal;
- said chip including one pin to which a conversion start signal (CONVST) can be applied from associated apparatus;
means to transmit an end-of-conversion signal (EOC);
said A/D circuitry including first terminal means to receive a convert-enable signal (CONVEN) for initiating a conversion and second terminal means to transmit a mode switchover signal (SLEEP) to place the A/D circuitry either in a normal-power mode or in a low-power mode in which the power consumed between conversions is substantially less than that consumed during a conversion operation;control circuitry for developing said CONVEN signal and said mode switchover signal, comprising; a first D-type flip-flop with reset; means applying a fixed signal to the D-terminal of said first D-type flip-flop; means connecting said CONVST signal to the clock input of said first D-type flip-flop; means connecting said EOC signal to the reset (R) terminal of said first D-type flip-flop; means connecting the Q output of said first D-type flip-flop to said first terminal means to initiate an analog-to-digital conversion in response to an output signal of said first D-type flip-flop; a second D-type flip-flop with set; means connecting the clock input of said second D-type flip-flop to the output of said first D-type flip-flop; means connecting said CONVST signal to the D input of said second D-type flip-flop; means connecting the complement of said CONVST signal to the set (S) terminal of said second D-type flip-flop; and means connecting the Q output of said second D-type flip-flop to said second terminal means to provide for low-power operation upon receipt of said Q output from said second D-type flip-flop. - View Dependent Claims (2, 3)
- said chip including one pin to which a conversion start signal (CONVST) can be applied from associated apparatus;
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4. An IC chip having A/D converter circuitry for converting an applied analog signal to a corresponding digital signal;
- said chip including one pin to which a conversion start signal (CONVST) can be applied from associated apparatus;
means to transmit an end-of-conversion signal (EOC);
means to transmit a BUSY signal when the A/D converter is carrying out a conversion;
said A/D circuitry including first terminal means to receive a convert-enable signal (CONVEN) for initiating a conversion and second terminal means to receive a mode switchover signal (SLEEP) to place the A/D circuitry either in a normal-power mode or in a low-power mode in which the power consumed between conversions is substantially less than that consumed during a conversion operation;control circuitry for developing said CONVEN signal and said mode switchover signal, comprising; first circuit means responsive to said CONVST signal for developing a CONVEN logic signal applied to said first terminal means to initiate an analog-to digital conversion; second circuit means for developing said SLEEP signal for said second terminal means and comprising; logic means receiving said BUSY signal and said CONVST signal and operable when said CONVST signal is of a predetermined logic status to produce said SLEEP signal so as to maintain normal power to said A/D converter at all times; said logic means serving when said CONVST signal is of a logic status opposite said predetermined logic status to produce said SLEEP signal so as to place said A/D converter in its low-power condition between conversions. - View Dependent Claims (5, 6)
- said chip including one pin to which a conversion start signal (CONVST) can be applied from associated apparatus;
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7. In an IC chip having A/D converter circuitry for converting an applied analog signal to a corresponding digital signal;
- said chip including one pin to which a conversion start (CONVST) control pulse can be applied from associated apparatus, said control pulse being either a first pulse of one polarity to provide for normal-power operation or alternatively a second pulse of opposite polarity to initiate low-power operation;
means to transmit an end-of-conversion signal (EOC);
said A/D circuitry including first terminal means to receive a convert-enable signal (CONVEN) for initiating a conversion and second terminal means to transmit a mode signal (SLEEP) to place the A/D circuitry in a low-power mode in which the power consumption between A/D conversions is substantially less than the power consumption rate during a conversion operation;control circuitry for developing said CONVEN signal and said mode signal, comprising; a first flip-flop having means to produce on an output terminal an output CONVEN signal responsive to and set by the voltage transition in a pre-selected direction of one of the two edges of said CONVST control pulse of said one polarity applied to said one pin of said chip; means directing said output CONVEN signal to said first terminal means to initiate an analog-to-digital conversion in response to said output CONVEN signal from said first flip-flop when said first flip-flop receives a CONVST pulse having a voltage transition of said pre-selected direction at said one edge thereof; means developing said EOC signal a preset time period after said CONVST control pulse to turn off said A/D converter; said first flip-flop being responsive to the other edge of said alternative CONVST control pulse of opposite polarity and having a voltage transition in said pre-selected direction, thereby activating said CONVEN signal and with it said A/D converter upon occurrence of said other edge of said alternative control pulse; and a second flip-flop responsive to said alternative CONVST control pulse and including means to apply a mode signal (SLEEP) to said second terminal means to provide for low-power operation at the time of said EOC signal after said alternative CONVST signal has been applied and has subsided. - View Dependent Claims (8, 9)
- said chip including one pin to which a conversion start (CONVST) control pulse can be applied from associated apparatus, said control pulse being either a first pulse of one polarity to provide for normal-power operation or alternatively a second pulse of opposite polarity to initiate low-power operation;
Specification