Fault detection for entire wafer stress test
First Claim
1. An integrated circuit die having a normal operation mode and at least one special test operation mode comprising:
- functional circuitry;
test enable logic circuitry;
a first test mode control input line extending to the edge of the die, coupled to the functional circuitry and to the test enable logic circuitry, for receiving a first test mode control signal;
a first and a second test enable input line extending to the edge of the die, for receiving a first and a second test enable signal, coupled to the test enable logic circuitry;
a power supply input line, coupled to the functional circuitry, for providing a power supply voltage thereto, extending to the edge of the die;
a test power supply input line extending to the edge of the die, for receiving a test power supply voltage; and
a switching transistor, having a conduction path connected on one end to the test power supply input and coupled on another end to the functional circuitry, and having a control terminal coupled to an output of the test enable logic circuitry, for applying the test power supply voltage to the functional circuitry responsive to the first test mode control input receiving the first test mode control signal and to the first and second test enable input lines receiving the first and the second test enable signals.
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0 Petitions
Accused Products
Abstract
A circuit and related method are provided for parallel stressing of a plurality of memory circuits integrated on dies on a silicon wafer. On each die, a test mode control circuit, having a first and a second test mode control inputs, and a test enable circuit, having a first and a second test enable inputs, are used to enable test operation mode and to force outputs of address buffers, data buffers and other signal buffers, like chip-enable or write buffers, to predetermined logic values so that all row and column decoders are selected and predetermined data is written into the memory cells. Contemporaneously are also exercised entire paths of buffers. The silicon wafer is then heated and maintained at an elevated temperature for a desired time, and then cooled down. In this way it is possible to stress test for ionic contamination, trap sites and weak oxides a plurality of integrated circuits on the same wafer in a short time, requiring only a limited number of test signals. During the test the current consumed by each die is monitored and, if a high current is consumed by one die, that die is isolated from the array of dies by controlling the test enable signals present in each row and column of the array. This circuit allows a parallel testing of a plurality of integrated circuits on a single wafer, reduces dramatically test times and avoids consequent burn in of packaged devices.
89 Citations
39 Claims
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1. An integrated circuit die having a normal operation mode and at least one special test operation mode comprising:
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functional circuitry; test enable logic circuitry; a first test mode control input line extending to the edge of the die, coupled to the functional circuitry and to the test enable logic circuitry, for receiving a first test mode control signal; a first and a second test enable input line extending to the edge of the die, for receiving a first and a second test enable signal, coupled to the test enable logic circuitry; a power supply input line, coupled to the functional circuitry, for providing a power supply voltage thereto, extending to the edge of the die; a test power supply input line extending to the edge of the die, for receiving a test power supply voltage; and a switching transistor, having a conduction path connected on one end to the test power supply input and coupled on another end to the functional circuitry, and having a control terminal coupled to an output of the test enable logic circuitry, for applying the test power supply voltage to the functional circuitry responsive to the first test mode control input receiving the first test mode control signal and to the first and second test enable input lines receiving the first and the second test enable signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An integrated circuit die having a normal operation mode and at least one special test operation mode comprising:
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functional circuitry; test enable logic circuitry; a first test mode control input line extending to the edge of the die, coupled to the functional circuitry and to the test enable logic circuitry, for receiving a first test mode control signal; a first and a second test enable input line extending to the edge of the die, for receiving a first and a second test enable signal, coupled to the test enable logic circuitry; a power supply input line, coupled to the functional circuitry, for providing a power supply voltage thereto, extending to the edge of the die; a first test power supply input line extending to the edge of the die, for receiving a first test power supply voltage; a second test power supply input line extending to the edge of the die, for receiving a second test power supply voltage; a first switching transistor, having a conduction path connected on one end to the first test power supply input and coupled on another end to the functional circuitry, and having a control terminal coupled to a first output of the test enable logic circuitry, for applying the first test power supply voltage to the functional circuitry responsive to the first test mode control input receiving the first test mode control signal and to the first test enable input line receiving the first test enable signal; and a second switching transistor, having a conduction path connected on one end to the second test power supply input and coupled on another end to the functional circuitry, and having a control terminal coupled to a second output of the test enable logic circuitry, for applying the second test power supply voltage to the functional circuitry responsive to the first test mode control input receiving the first test mode control signal and to the second test enable input line receiving the second test enable signal. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A method for stress testing a plurality of integrated circuits, integrated on a silicon wafer and arranged in rows and columns, each integrated circuit having
a test enable circuit, a power supply input and a first input of the test enable circuit connected to like inputs of others of the plurality of integrated circuits by way of conductive lines running in a first direction between the integrated circuits, a test power supply input and a second input of the test enable circuit connected to like inputs of others of the plurality of integrated circuits by way of conductive lines running in a second direction between the integrated circuits, comprising the steps of: -
monitoring the current consumed by each of the plurality of integrated circuits by monitoring the current flowing in conductive lines used to supply the integrated circuits; disabling each integrated circuit on which is detected an abnormal high current in the monitoring step; and applying a stress voltage to the conductive lines running in the first and in the second direction associated with the power supply input and the test power supply input. - View Dependent Claims (27, 28, 29, 30, 31)
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32. A method for stress testing a plurality of integrated circuits, integrated on a silicon wafer and arranged in rows and columns, each integrated circuit having
a test enable circuit, a first and a second test mode input connected to conductive lines running between the integrated circuits, a power supply input, a first test power supply input and a first input of the test enable circuit connected to like inputs of others of the plurality of integrated circuits by way of conductive lines running in a first direction between the integrated circuits, a second test power supply input and a second input of the test enable circuit connected to like inputs of others of the plurality of integrated circuits by way of conductive lines running in a second direction between the integrated circuits, comprising the steps of: -
monitoring the current consumed by each of the plurality of integrated circuits by monitoring the current flowing in conductive lines running in the first and in the second direction connected with the first and the second test power supply inputs; disabling each integrated circuit on which is detected an abnormal high current in the monitoring step; and applying a stress voltage to the conductive lines running in the first and in the second direction associated with the power supply input and the test power supply input. - View Dependent Claims (33, 34, 35, 36, 37, 38)
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39. A silicon wafer including:
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a plurality of dies arranged in rows and columns on which are integrated a plurality of integrated circuits, each integrated circuit having functional circuitry, test enable logic circuitry, a switching transistor and control inputs extending to the edge of the die, and operable in a normal operation mode and at least one special test operation mode; control lines running between the dies and connected to corresponding control inputs of some of the plurality of integrated circuits for applying control signals to the integrated circuits for enabling and controlling the at least one special test operation mode; and test power supply lines running between the dies and connected to corresponding control inputs of some of the plurality of integrated circuits, for receiving a test power supply voltage on each test power supply line; wherein each switching transistor has a conduction path connected on one end to one of the test power supply lines and coupled on another end to the functional circuitry, and having a control terminal coupled to an output of the test enable logic circuitry, for applying the test power supply voltages to the functional circuitry responsive to the corresponding control inputs receiving corresponding control signals.
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Specification