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Fault detection for entire wafer stress test

  • US 5,619,462 A
  • Filed: 07/31/1995
  • Issued: 04/08/1997
  • Est. Priority Date: 07/31/1995
  • Status: Expired due to Term
First Claim
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1. An integrated circuit die having a normal operation mode and at least one special test operation mode comprising:

  • functional circuitry;

    test enable logic circuitry;

    a first test mode control input line extending to the edge of the die, coupled to the functional circuitry and to the test enable logic circuitry, for receiving a first test mode control signal;

    a first and a second test enable input line extending to the edge of the die, for receiving a first and a second test enable signal, coupled to the test enable logic circuitry;

    a power supply input line, coupled to the functional circuitry, for providing a power supply voltage thereto, extending to the edge of the die;

    a test power supply input line extending to the edge of the die, for receiving a test power supply voltage; and

    a switching transistor, having a conduction path connected on one end to the test power supply input and coupled on another end to the functional circuitry, and having a control terminal coupled to an output of the test enable logic circuitry, for applying the test power supply voltage to the functional circuitry responsive to the first test mode control input receiving the first test mode control signal and to the first and second test enable input lines receiving the first and the second test enable signals.

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