Integrated circuit device and test method therefor

• US 5,619,463 A
• Filed: 08/24/1995
• Issued: 04/08/1997
• Est. Priority Date: 08/26/1994
• Status: Expired due to Term

• Current Assignee: SGS Thomson Microelectronics Ltd (STMicroelectronics NV)
• Original Assignee: SGS Thomson Microelectronics Ltd (STMicroelectronics NV)
• Inventors: Malhi, Vijay
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/518,422
• Time in Patent Office: 593 Days
• Field of Search: 365/233.5, 365/222, 365/201, 365/193, 365/236, 365/189.02, 365/233, 324/763, 324/765, 324/73.1, 395/800
• US Class Current: 365/201
• CPC Class Codes: G01R 31/30 Marginal testing, e.g. by varying supply voltage testing computers during standby operation or idle time G06F11/22
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders

Abstract

An integrated circuit device includes an oscillator; a counter; a switch for selectively connecting the oscillator to the counter in a test mode; and an output circuit for providing the output count generated by the counter for determining the frequency of the oscillator. Thus, use is made of the normal on-chip counter in an integrated circuit to provide a reliable way of measuring the frequency of the on-chip oscillator.

Claims

1. An integrated circuit device, operable in a normal mode and a test mode, the device being testable in association with a tester, including:

an oscillator arranged to produce a periodic output signal for controlling operations of the device, during the normal mode of operation;

a counter having an input for receiving a timing signal representing operations of the device, during the normal mode of operation, and arranged to count transitions in said periodic output signal to generate an output count during the test mode of operation;

switch circuitry for selectively connecting said periodic output signal of the oscillator to the input of the counter in the test mode of operation, said test mode being implemented for a predetermined time; and

an output circuit for providing the output count generated by said counter after said predetermined time to the tester so that the tester can derive the frequency of the oscillator from said output count and said predetermined time.

2. An integrated circuit device according to claim 1 which is implemented on a single chip and wherein the output circuit comprises at least one output pin for transmitting said output count to a tester which is off-chip.

3. An integrated circuit device according to claim 1 or 2 wherein the switch circuitry is connected to received said periodic output signal from the oscillator and is operable to inhibit transmission of said periodic output signal to said counter, during the normal mode of operation, and to allow transmission of said periodic output signal to said counter in the test mode of operation.

4. An integrated circuit device according to claim 1 or 2 wherein the switch circuitry is operable to connect said periodic output signal of the oscillator either to a circuit for controlling operations of the device during the normal mode of operation or to said counter during the test mode of operation.

5. An integrated circuit device according to claim 1 wherein the oscillator has an enable input which is enabled for said predetermined time by selection of said test mode.

6. An integrated circuit device according to claim 1 which comprises a test bus and a test multiplexor operable to connect the output of said counter onto the test bus during said test mode of operation.

7. An integrated circuit device according to claim 6 wherein said output circuit is connected to the test bus, during said test mode of operation, via an output multiplexor.

8. An integrated circuit device according to claim 1 wherein the output count generated by the counter after said predetermined time is stored and is available in response to control address signals.

9. An integrated circuit device according to claim 8 wherein the output count generated by the counter is in the form of a plurality of bits wherein the number of bits is greater than the capacity of the test bus, said integrated circuit device further comprising circuitry for transmitting said output count to said tester over a plurality of address cycles.

10. An integrated circuit device according to claim 8 or 9 which comprises an address pin via which said control address signals are supplied.

11. An integrated circuit device according to claim 1 wherein said switch circuitry is connected to receive a test mode implementation signal from an address pin of the integrated circuit device.

12. An integrated circuit device according to claim 1 which includes a memory having addressable locations, and wherein the frequency of the oscillator derived from said tester is stored at said addressable locations within said memory.

13. A memory device, operable in a normal mode and a test mode, the device being testable in association with a tester, including:

an array of memory cells;

decode circuitry to selectively access memory cells in said array;

an oscillator arranged to produce a periodic output signal for controlling operations of the memory device during the normal mode of operation;

a counter having an input for receiving a timing signal representing operations of the memory device, during the normal mode of operation, and arranged to count transitions in said periodic output signal to generate an output count during the test mode of operation;

switch circuitry for selectively connecting said periodic output signal of the oscillator to the input of the counter during the test mode of operation, said test mode being implemented for a predetermined time; and

an output circuit for providing the output count generated by said counter after said predetermined time to the tester so that the tester can derive the frequency of the oscillator from said output count and said predetermined time.

14. A method of characterizing an integrated circuit device comprising the steps of:

enabling an oscillator, provided within the integrated circuit device for controlling operations during a normal mode of operation of the device, for a predetermined time during a test mode of operation so that the oscillator produces a periodic output signal for said predetermined time;

connecting said periodic output signal to the input of a counter, which is provided within said integrated circuit device for representing operations of the device in the normal mode of operation, said counter being arranged to count transitions in said periodic output signal to generate an output count during the test mode of operation; and

supplying said output count to a tester capable of deriving the frequency of the oscillator from said output count and said predetermined time.

15. A test method according to claim 14 wherein the integrated circuit device is implemented on a single chip and wherein said tester is off-chip.

16. A test method according to claim 14 or 15 when used to test an integrated circuit device comprising a test bus and a test multiplexor, said method further comprising a step of connecting the output of said counter onto said test bus via said test multiplexor to supply said output count to the tester.

17. A test method according to claim 14 wherein the output count generated by the counter after said predetermined time is stored and is available in response to control address signals.

18. A test method according to claim 17 wherein said output count is supplied as a plurality of bits wherein the number of bits is greater than the capacity of the test bust and wherein said output count is transmitted to said tester over a plurality of address cycles.

19. A test method according to claim 17 or 18 wherein said control address signals are supplied via an address pin of the integrated circuit device.

20. A test method according to claim 14 wherein a test mode is implemented by application of a signal to an address pin of the integrated circuit device.

21. A test method according to claims 14 wherein the device includes a memory having addressable locations, and the frequency of the oscillator derived by the tester is stored at the addressable locations within the memory.

22. An integrated circuit device, operable in a normal mode and a test mode, the device being testable in association with a tester, including:

an oscillator arranged to produce a periodic output signal to control operations of the device during the normal mode of operation;

a counter having an input for receiving, during the normal mode of operation, a timing signal representing operations of the device, and arranged to count transitions in said periodic output signal to generate an output count during the test mode of operation;

switch circuitry for selectively connecting said periodic output signal of the oscillator to the input of the counter in the test mode of operation, said test mode being implemented for a predetermined time; and

an output circuit for providing the output count generated by said counter after said predetermined time to the tester; and

wherein the device is implemented on a single chip and the output circuit comprises at least one output pin for transmitting said output count to the tester which is off-chip.

23. A method of testing an integrated circuit device comprising the steps of:

enabling an oscillator, provided within the integrated circuit device for controlling operations during a normal mode of operation of the device, for a predetermined time during a test mode of operation so that the oscillator produces a periodic output signal for said predetermined time;

connecting said periodic output signal to the input of a counter, which is provided within said integrated circuit device for counting operations of the device in the normal mode of operation, said counter being arranged to count transitions in said periodic signal to generate an output count during the test mode of operation; and

supplying said output count to a tester capable of deriving the frequency of the oscillator from said output count and said predetermined time; and

wherein the integrated circuit device is implemented on a single chip and said tester is off-chip.

24. A method of testing an integrated circuit device, comprising steps of:

(A) counting a number of pulses on a periodic signal generated on the device;

(B) providing at least one test signal to the device from an external tester to enable the counting in step (A), the duration of the counting being determined by the at least one test signal;

(C) providing the counted number to the external tester; and

(D) calculating a frequency of the periodic signal in the external tester.

25. The method of claim 24, wherein the step (A) comprises a step of:

counting the number of pulses on an oscillator provided on the integrated circuit device for use during a normal mode of operation.

26. A method of testing an integrated circuit device, the method comprising steps of:

(A) counting a number of oscillations of an oscillating signal provided by an oscillating circuit, the oscillating signal being used by and for the operation of the integrated circuit device in a normal mode of operation, the counting occuring over a period of time; and

(B) calculating a frequency of the oscillating circuit based on the number of oscillations counted and the length of the period of time.

27. The method of claim 26, wherein:

the step (A) comprises a step of counting the number of oscillations of the oscillating signal during a test mode of operation for the period of time, the period of time being controlled by an external tester; and

the step (B) is performed by the external tester.