Two-stage memory refresh circuit

• US 5,619,468 A
• Filed: 12/07/1995
• Issued: 04/08/1997
• Est. Priority Date: 12/07/1995
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Ghosh, Atish, Pencis, Jennifer B.
• Primary Examiner(s): YOO, DO H
• Application Number:
  US08/568,848
• Time in Patent Office: 488 Days
• Field of Search: 365/222, 365/236, 365/233
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles

Abstract

A timing refresh circuit refreshes a timed circuit in a functionally equivalent manner, whether the timing refresh circuit is operated at a high frequency or a low frequency. The two-stage timing refresh circuit includes a counter and combinational logic, in combination, connected between a refresh timing signal generator and a control circuit. The counter is incremented for each refresh timing signal and decremented for each refresh cycle realized by the control circuit. The combinational logic converts the counter count to a refresh signal by generating a refresh request to the control circuit whenever a count is pending in the counter.

Claims

1. A timing control circuit for controlling timing signals to a fixed-timing circuit in a variable-time system, the fixed-timing circuit having an input terminal for receiving a timing signal and an output terminal for generating a timing signal indicative of fixed-timing circuit timing, the fixed-timing circuit being accessible to timing signals of the timing control circuit in a first state and inaccessible to timing signals of the timing control circuit in a second state, the timing control circuit comprising:

a fixed timing signal generator;

a counter having a first input terminal coupled to the fixed timing signal generator, a second input terminal coupled to the output terminal of the fixed-timing circuit and a plurality of output bit lines; and

a combinational logic circuit having a plurality of input bit lines coupled to the plurality of output bit lines of the counter and an output line coupled to the input terminal of the fixed-timing circuit.

2. A timing control circuit according to claim 1, wherein:

the counter is an up/down counter;

the first input terminal of the counter is an up-count terminal; and

the second input terminal of the counter is a down-count terminal.

3. A timing control circuit according to claim 1 wherein:

the fixed-timing circuit is a DRAM circuit including a DRAM controller;

the combinational logic circuit output line carries a refresh request signal; and

the counter second input terminal is coupled to the DRAM circuit to receive a refresh cycle signal.

4. A timing control circuit according to claim 1 wherein:

the combinational logic circuit is a multiple-input OR gate for selecting a selected count of the counter.

5. A timing refresh control circuit for controlling timing signals to a fixed-timing DRAM circuit in a variable-time system, the fixed-timing DRAM circuit having an input terminal for receiving a timing signal and an output terminal for generating a timing signal indicative of fixed-timing circuit timing, the fixed-timing DRAM circuit being accessible to timing signals of the timing refresh control circuit in a first state and inaccessible to timing signals of the timing refresh control circuit in a second state, the timing refresh control circuit comprising:

a fixed timing refresh clock signal generator;

a counter having a first input terminal coupled to the fixed timing refresh clock signal generator, a second input terminal coupled to the output terminal of the fixed-timing DRAM circuit and a plurality of output bit lines; and

a combinational logic circuit having a plurality of input bit lines coupled to the plurality of output bit lines of the counter and a refresh cycle output line coupled to the input terminal of the fixed-timing DRAM circuit.

6. A timing refresh control circuit according to claim 5, wherein:

the counter is an up/down counter;

the first input terminal of the counter is an up-count terminal; and

the second input terminal of the counter is a down-count terminal.

7. A timing refresh control circuit according to claim 5 wherein:

the combinational logic circuit is a multiple-input OR gate for selecting a selected count of the counter.

8. A circuit board for operating at emulation speed in a first operating state and for operating at a circuit speed in a second operating state, the circuit board comprising:

a fixed-timing circuit having an input terminal for receiving a timing signal and an output terminal for generating a timing signal indicative of fixed-timing circuit timing, the fixed-timing circuit being accessible to signals of the circuit board in a first state and inaccessible to timing signals of the circuit board in a second state;

a fixed timing signal generator;

a counter having a first input terminal coupled to the fixed timing signal generator, a second input terminal coupled to the output terminal of the fixed-timing circuit and a plurality of output bit lines; and

a combinational logic circuit having a plurality of input bit lines coupled to the plurality of output bit lines of the counter and an output line coupled to the input terminal of the fixed-timing circuit.

9. A circuit board according to claim 8, wherein:

the counter is an up/down counter;

the first input terminal of the counter is an up-count terminal; and

the second input terminal of the counter is a down-count terminal.

10. A circuit board according to claim 8 wherein:

the fixed-timing circuit is a DRAM circuit including a DRAM controller;

the combinational logic circuit output line carries a refresh request signal; and

the counter second input terminal is coupled to the DRAM circuit to receive a refresh cycle signal.

11. A circuit board according to claim 8 wherein:

the combinational logic circuit is a multiple-input OR gate for selecting a selected count of the counter.

12. A method of controlling timing signals to a fixed-timing circuit in a variable-time system, the fixed-timing circuit having an input terminal for receiving a timing signal and an output terminal for generating a timing signal indicative of fixed-timing circuit timing, the fixed-timing circuit being accessible to timing signals in a first state and inaccessible to timing signals in a second state, the method comprising the steps of:

generating a fixed timing signal;

incrementing a count of the number of fixed timing signals;

decrementing the count by the number of signals indicative of fixed-timing circuit timing;

applying the fixed timing signal to the fixed-timing circuit when the count is greater than one; and

terminating application of the fixed timing signal to the fixed-timing circuit when the count is decremented to zero.

13. A method according to claim 12 wherein:

the fixed-timing circuit is a DRAM circuit including a DRAM controller;

the fixed timing signal is a refresh request signal; and

the timing signal indicative of fixed-timing circuit timing is a refresh cycle signal.

14. A method of providing a timing control circuit for controlling timing signals to a fixed-timing circuit in a variable-time system, the fixed-timing circuit having an input terminal for receiving a timing signal and an output terminal for generating a timing signal indicative of fixed-timing circuit timing, the fixed-timing circuit being accessible to timing signals of the timing control circuit in a first state and inaccessible to timing signals of the timing control circuit in a second state, the method comprising the steps of:

providing a fixed timing signal generator;

providing a counter having a first input terminal coupled to the fixed timing signal generator, a second input terminal coupled to the output terminal of the fixed-timing circuit and a plurality of output bit lines; and

providing a combinational logic circuit having a plurality of input bit lines coupled to the plurality of output bit lines of the counter and an output line coupled to the input terminal of the fixed-timing circuit.

15. A method according to claim 14, wherein:

the counter is an up/down counter;

the first input terminal of the counter is an up-count terminal; and

the second input terminal of the counter is a down-count terminal.

16. A method according to claim 14 wherein:

the fixed-timing circuit is a DRAM circuit including a DRAM controller;

the combinational logic circuit output line carries a refresh request signal; and

the counter second input terminal is coupled to the DRAM circuit to receive a refresh cycle signal.

17. A method according to claim 14 wherein:

the combinational logic circuit is a multiple-input OR gate for selecting a selected count of the counter.