Integrated network switch having mixed mode switching with selectable full frame/half frame switching

• US 5,619,496 A
• Filed: 08/28/1995
• Issued: 04/08/1997
• Est. Priority Date: 06/10/1994
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Weir, Steven
• Primary Examiner(s): TON, DANG T
• Application Number:
  US08/520,004
• Time in Patent Office: 589 Days
• Field of Search: 370/66, 370/60.1, 370/60, 370/94.1, 370/94.2, 370/61, 370/67, 370/68, 370/118, 370/84, 370/85.7, 370/85.1, 370/85.12, 370/95.1, 370/95.2, 370/95.3, 370/58.1 , 370/58.2, 370/58.3, 370/77, 370/85.6, 370/62, 370/13, 370/17, 370/105.1, 370/110.1, 340/825.01, 340/825.02, 340/825.03, 340/825.5, 340/825.51, 379/202, 379/229, 379/237, 379/240, 375/242, 375/222, 375/225, 375/211, 395/821, 395/823, 395/827, 395/828, 395/831, 395/833, 395/834, 395/840, 395/850, 395/851, 395/853, 395/864
• US Class Current: 370/363
• CPC Class Codes: H04Q 11/0407 using a stored programme control
• CPC Class Codes: H04Q 11/0414 Details
• CPC Class Codes: H04Q 2213/13003 Constructional details of switching devices
• CPC Class Codes: H04Q 2213/1302 Relay switches
• CPC Class Codes: H04Q 2213/13034 A/D conversion, code compression/expansion
• CPC Class Codes: H04Q 2213/1304 Coordinate switches, crossbar, 4/2 with relays, coupling field
• CPC Class Codes: H04Q 2213/1308 Power supply
• CPC Class Codes: H04Q 2213/13103 Memory
• CPC Class Codes: H04Q 2213/13106 Microprocessor, CPU
• CPC Class Codes: H04Q 2213/13213 Counting, timing circuits
• CPC Class Codes: H04Q 2213/13292 Time division multiplexing, TDM
• CPC Class Codes: H04Q 2213/13299 Bus
• CPC Class Codes: H04Q 2213/1332 Logic circuits
• CPC Class Codes: H04Q 2213/13322 Integrated circuits
• CPC Class Codes: H04Q 2213/13405 Dual frequency signaling, DTMF

Abstract

An integrated network switch operable in either full-frame or half-frame switching modes on a circuit-by-circuit basis. To effect selective operation in either full-frame or half-frame switching modes an information memory buffer has the capacity of storing two samples per port. A connection memory contains the source addresses for the output ports. The most significant bit of an address designates the first or second sample of the two sample information memory buffer. For half-frame mode operation, the current value of the most significant bit of the write pointer (the address being written to) is used in the source address for reading when the source address is less than the write pointer. However, when the source address is greater than the write pointer, the most significant bit position is switched. For full-frame mode operation, the most significant bit of the source address will always take the inverse of the most significant bit for the write pointer. This assures that the read frame is always in the half of the two sample buffer not then being written to.

Claims

1. In an integrated network switch including ports for connection to peripheral devices, and switching apparatus for selectively switching signals organized in frame format between ports, each of said ports occupying a fixed time slot in the frame, apparatus for selectively switching said signals in either full-frame or half-frame format comprising;

an information memory for storing source data from said ports,

a connection memory for storing port-port connection data,

a time slot counter for providing time slot information to the information memory and the connection memory, each time slot being associated with a unique memory address in the information memory,

said information memory having at least two memory cells associated with each time slot, and

means for selectively switching said signals organized in frame format according to one of a half-frame mode of operation or full-frame mode of operation.

2. The integrated network switch of claim 1 wherein said means for selectively switching between said half-frame and full-frame modes of operation includes;

a write pointer counter for designating the address of a write pointer,

a comparator for comparing the magnitude of the write pointer with a source address,

a function register for receiving the output from the magnitude comparator and a predesignated bit from the source address, the predesignated bit defining one of the half-frame mode of operation and the full-frame mode of operation, the function register also receiving the most significant bit of the write pointer, the output of the function register defining a first or second memory cell of the information memory corresponding to a time slot.

3. For an integrated network switch operable in either a full-frame mode of operation or half-frame mode of operation, a time slot interchanger comprising;

an information memory for storing data received from source ports of the integrated network switch at memory location associated with the source ports, said information memory having first and second memory cells for each source port whereby the information memory can store at least two frames of data from source ports, the first memory cell storing data from a first frame and the second memory cell storing data from a second frame,

means for selectively reading out data stored in said information memory at time slots corresponding to destination ports thereby achieving port-port communication,

a connection memory for storing port-port connection information indicating the routing of information from a source port to a destination port, and

means responsive to information stored in said connection memory for reading out data stored in said information memory in time slots corresponding to destination ports for the stored data and from either said first memory cell or said second memory cell in accordance with whether the integrated network switch is operating in the half-frame mode of operation or full-frame mode of operation.

4. The time slot interchanger of claim 3 further comprising means for indicating whether a source port is operable in the half-frame mode or full-frame mode of operation, and wherein said means for reading out stored data from said information memory operates responsive to said means for indicating.

5. An integrated network switch including a multi-frame information memory for storing multi-frame information in at least first and second memory cells at memory locations corresponding to source ports and a connection memory storing for each destination port a information memory source port address, the improvement comprising:

means for operating the integrated network switch in a half-frame operating mode,

means for operating the integrated network switch in a full-frame operating mode, and

means for selectively enabling the half-frame operating mode means and the full-frame operating mode means,

wherein a write pointer designates a memory location including a memory cell of said information memory to be written to from a source port, said means for operating in the full-frame operating mode includes means for always reading from the memory cell storing information from a frame prior to the frame being written according to the write pointer.

6. An integrated network switch including a multi-frame information memory for storing multi-frame information in at least first and second memory cells at memory locations corresponding to source ports and a connection memory storing for each destination port a information memory source port address, the improvement comprising:

means for operating the integrated network switch in a half-frame operating mode,

means for operating the integrated network switch in a full-frame operating mode, and

means for selectively enabling the half-frame operating mode means and the full-frame operating mode means,

wherein a write pointer designates a memory location including a memory cell of said information memory to be written to from a source port, said means for operating in the half-frame operating mode includes means for reading from either a frame prior to the frame being written according to the write pointer or from the frame being written according to the write pointer depending on whether a source address designating a memory location to be read to a destination port is greater than or less than the address designated by the write pointer.

7. For an integrated network switch including a multi-frame information memory for storing multi-frame information in at least first and second memory cells at memory locations corresponding to source ports and a connection memory storing for each destination port a information memory source port address, a method for retrieving information data from said information memory comprising:

selectively operating the integrated network switch in a half-frame operating mode or a full-frame operating mode, and

providing an indicator as part of the data received from the source ports to enable the half-frame operating mode or the full-frame operating mode depending on the state of the indicator

further including the steps of;

providing a write pointer which designates a memory location including a memory cell of said information memory to be written to from a source port, and

operating in the full-frame operating mode by always reading from the memory cell storing information from a frame prior to the frame being written according to the write pointer.

8. For an integrated network switch including a multi-frame information memory for storing multi-frame information in at least first and second memory cells at memory locations corresponding to source ports and a connection memory storing for each destination port a information memory source port address, a method for retrieving information data from said information memory comprising:

selectively operating the integrated network switch in a half-frame operating mode or a full-frame operating mode, and

providing an indicator as part of the data received from the source ports to enable the half-frame operating mode or the full-frame operating mode depending on the state of the indicator,

further including the steps of;

providing a write pointer which designates a memory location including a memory cell of said information memory to be written to from a source port,

operating in the half-frame operating mode by reading from either a frame prior to the frame being written according to the write pointer or from the frame being written according to the write pointer depending on whether a source address designating a memory location to be read to a destination port is greater than or less than the address designated by the write pointer.