Fault tolerant memory system which utilizes data from a shadow memory device upon the detection of erroneous data in a main memory device
First Claim
1. A fault tolerant memory system, comprising:
- a main memory device, storing data and an associated parity checking code;
a shadow memory device, storing data corresponding to the data stored in the main memory;
a multiplexer, responsive to a control signal having a first state for coupling data from the main memory device to an output terminal, and responsive to the control signal having a second state for coupling data from the shadow memory device to the output terminal; and
a controller comprising;
a comparator having a first input terminal responsive to the data from the main memory device, a second input terminal responsive to the data from the shadow memory device, a first output terminal producing a first output signal having a first state when the data from the main memory device is the same as the data from the shadow memory device and a second state otherwise, and a second output terminal producing a second output signal having a first state when only a single bit is different between the data from the main memory device and the data from the shadow memory device, and a second state otherwise;
a parity error detecting circuit having a first input terminal responsive to the data from the main memory device, a second input terminal responsive to the associated error detecting code from the main memory device, and an output terminal producing a signal having a first state when an error is detected, and a second state otherwise; and
a logic circuit having a first input terminal responsive to the first output terminal of the comparator, a second input terminal responsive to the second output signal of the comparator, a third input terminal coupled to the output terminal of the parity error detecting circuit, and an output terminal which generates the control signal having the first state when the first output signal from the comparator has the first state, generates the control signal having the first state when the first output signal from the comparator has the second state, the second output signal from the comparator has the first state, and the signal from the error detecting circuit has the second state, generates the control signal having the second state when the first output signal from the comparator has the second state, the second output signal from the comparator has the first state, and the signal from the error detecting circuit has the first state, and generates a status signal, indicating an uncorrectable-read-error when both the first and second output signals from the comparator have the second state.
1 Assignment
0 Petitions
Accused Products
Abstract
A fault tolerant memory system is disclosed which includes a main memory device, storing data and an associated error detecting code, and a shadow memory device, storing data corresponding to the data stored in the main memory. A multiplexer, selectively couples data from either the main memory device or the shadow memory device to an output terminal in response to a control signal. A controller reads the data and associated error detecting code from the main memory device and the corresponding data from the shadow memory device, and generates the multiplexer control signal such that the multiplexer couples data from the shadow memory device to the output terminal if the data from the main memory device is not the same as the data from the shadow memory device and the error detecting code indicate an error in the data from the main memory device, and otherwise couples the data from the main memory device to the output terminal.
149 Citations
6 Claims
-
1. A fault tolerant memory system, comprising:
-
a main memory device, storing data and an associated parity checking code; a shadow memory device, storing data corresponding to the data stored in the main memory; a multiplexer, responsive to a control signal having a first state for coupling data from the main memory device to an output terminal, and responsive to the control signal having a second state for coupling data from the shadow memory device to the output terminal; and a controller comprising; a comparator having a first input terminal responsive to the data from the main memory device, a second input terminal responsive to the data from the shadow memory device, a first output terminal producing a first output signal having a first state when the data from the main memory device is the same as the data from the shadow memory device and a second state otherwise, and a second output terminal producing a second output signal having a first state when only a single bit is different between the data from the main memory device and the data from the shadow memory device, and a second state otherwise; a parity error detecting circuit having a first input terminal responsive to the data from the main memory device, a second input terminal responsive to the associated error detecting code from the main memory device, and an output terminal producing a signal having a first state when an error is detected, and a second state otherwise; and a logic circuit having a first input terminal responsive to the first output terminal of the comparator, a second input terminal responsive to the second output signal of the comparator, a third input terminal coupled to the output terminal of the parity error detecting circuit, and an output terminal which generates the control signal having the first state when the first output signal from the comparator has the first state, generates the control signal having the first state when the first output signal from the comparator has the second state, the second output signal from the comparator has the first state, and the signal from the error detecting circuit has the second state, generates the control signal having the second state when the first output signal from the comparator has the second state, the second output signal from the comparator has the first state, and the signal from the error detecting circuit has the first state, and generates a status signal, indicating an uncorrectable-read-error when both the first and second output signals from the comparator have the second state.
-
-
2. A fault tolerant memory system, comprising:
-
a main memory device, storing data partitioned into a plurality of data groups, each data group having a parity bit associated with it; a shadow memory device, storing data corresponding to the data stored in the main memory, and partitioned into a plurality of data groups respectively corresponding to data groups in the main memory device; a multiplexer, responsive to a control signal having a first state for coupling data from the main memory device to the output terminal, and responsive to the control signal having a second state for coupling data from the shadow memory device to the output terminal; and a controller, comprising; a comparator having a plurality of comparing circuits each responsive to a respective one of the corresponding data groups in the main memory device and the shadow memory device, for generating a first output signal having a first state when the corresponding data groups from the main memory device and the shadow memory device are the same and a second state otherwise, and a second output signal having a first state when only a single bit is different between the corresponding data groups from the main memory device and the shadow memory device, and a second state otherwise; a parity checking circuit having a first input terminal responsive to the data from the main memory device, a second input terminal responsive to the associated parity code from the main memory device, and an output terminal producing a signal having a first state when an error is detected, and a second state otherwise; and a logic circuit, responsive to the first and second output signals of the plurality of comparing circuits, having an input terminal coupled to the output terminal of the parity checking circuit, and having an output terminal producing the control signal having the first state when the first output signal from any one of the comparing circuits has the second state, the second output signal from the one of the comparing circuits has the first state, and the signal from the parity checking circuit has the second state and generates the control signal having the second state when the first output signal from any one of the comparing circuits has the second state, the second output signal from the one of the comparing circuits has the first state, and the signal from the parity checking circuit has the first state. - View Dependent Claims (3, 4, 5, 6)
-
Specification