Sapphireless group III nitride semiconductor and method for making same

• US 5,620,557 A
• Filed: 06/26/1995
• Issued: 04/15/1997
• Est. Priority Date: 12/27/1993
• Status: Expired due to Fees

• Current Assignee: Hiroshi Amano, Isamu Akasaki, Toyoda Gosei Company Limited (Toyota Motor Corporation)
• Original Assignee: Toyoda Gosei Company Limited (Toyota Motor Corporation)
• Inventors: Kato, Hisaki, Koike, Masayoshi, Amano, Hiroshi, Manabe, Katsuhide, Akasaki, Isamu, Koide, Norikatsu
• Primary Examiner(s): POWELL, WILLIAM A
• Application Number:
  US08/494,846
• Time in Patent Office: 659 Days
• Field of Search: 216/36, 216/76, 216/101, 156/631.1, 156/632.1, 156/662.1, 156/655.1, 437/86, 437/974
• US Class Current: 438/507
• CPC Class Codes: C30B 25/02 Epitaxial-layer growth
• CPC Class Codes: C30B 29/403 AIII-nitrides
• CPC Class Codes: C30B 29/406 Gallium nitride
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: Y10S 117/915 Separating from substrate

Abstract

A method of manufacturing two sapphireless layers (3a, 3b) at one time made of Group III nitride compound semiconductor satisfying the formula Al_x Ga_y In_1-x-y N, inclusive of x=0, y=0, and x=y=0, and a LED (10) utilizing one of the semiconductor layers (3a, 3b) as a substrate (3) includes the steps of forming two zinc oxide (ZnO) intermediate layers (2a, 2b) on each side of a sapphire substrate (1), forming two Group III nitride compound semiconductor layers (3a, 3b) satisfying the formula Al_x Ga_y In_1-x-y N, inclusive of x=0, y=0, and x=y=0, each laminated on each of the intermediate ZnO layers (2a, 2b), and separating the intermediate ZnO layers (2a, 2b) from the sapphire substrate (1) by etching with an etching liquid only for the ZnO layers (2a, 2b). At least one of the so-obtained Group III nitride compound layers is provided with n and p MOVPE layers (4, 5) formed thereon with electrodes (6, 7) on opposite sides to form an LED emitting in the 450 nm region and having a low device resistance.

Claims

1. A method for manufacturing a gallium nitride (GAN) sapphireless semiconductor film, comprising the steps of:

forming zinc oxide (ZnO) layers on respective ones of at least two sides of a sapphire substrate;

forming semiconductor layers of Group III nitride compound semiconductor satisfying the formula Al_x Ga_y In_1-x-y N, inclusive of x=0, y=0, and x=y=0 on respective ones of said ZnO layers;

etching said ZnO layers with a ZnO-specific etchant; and

separating said semiconductor layers from said sapphire substrate.

3. The method of claim 1, wherein said ZnO layers have a thickness of 10 nm to 1 μ

m each.

5. The method of claim 1, wherein at least one of said semiconductor layers comprises an n-layer of n-type nitrogen-Group III compound semiconductor satisfying the formula Al_x Ga_y In_1-x-y N, inclusive of x=0, y=0, and x=y=0, and a p-layer of p-type nitrogen-Group III compound semiconductor satisfying the formula Al_x Ga_y In_1-x-y N, inclusive of x=0, y=0, and x=y=0.

7. The method of claim 1, wherein at least one of said semiconductor layers comprises two n-layers of n-type nitrogen-Group III compound semiconductor satisfying the formula Al_x Ga_y In_1-x-y N, inclusive of x=0, y=0, and x=y=0, and a p-layer of p-type nitrogen-Group III compound semiconductor satisfying the formula Al_x Ga_y In_1-x-y N, inclusive of x=0, y=0, and x=y=0, said two n-layers having different electron concentrations from each other.

9. The method of claim 1, wherein said at least two sides of said sapphire substrate are opposing sides of said sapphire substrate.

11. The method of claim 1, further comprising the steps of:

forming a GaN buffer layer on a side of one of said semiconductor layers;

forming a GaN i-layer on said GaN buffer layer;

irradiating said GaN i-layer with electrons so as to form a p-layer having p-type conduction.

12. The method of claim 11, further comprising the steps of:

forming a first electrode on said semiconductor layer and a second electrode on said p-layer.

2. A semiconductor produced by:

forming zinc oxide (ZnO) layers on respective ones of at least two sides of a sapphire substrate;

forming semiconductor layers of Group III nitride compound semiconductor satisfying the formula Al_x Ga_y In_1-x-y N, inclusive of x=0, y=0, and x=y=0 on respective ones of said ZnO layers;

etching said ZnO layers with a ZnO-specific etchant; and

separating said semiconductor layers from said sapphire substrate.

4. The semiconductor of claim 2, wherein said ZnO layers have a thickness of 10 nm to 1 μ

m each.

6. The semiconductor of claim 2, wherein at least one of said semiconductor layers comprises an n-layer of n-type nitrogen-Group III compound semiconductor satisfying the formula Al_x Ga_y In_1-x-y N, inclusive of x=0, y=0, and x=y=0, and a p-layer of p-type nitrogen-Group III compound semiconductor satisfying the formula Al_x Ga_y In_1-x-y N, inclusive of x=0, y=0, and x=y=0.

8. The semiconductor of claim 2, wherein at least one of said semiconductor layers comprises two n-layers of n-type nitrogen-Group III compound semiconductor satisfying the formula Al_x Ga_y In_1-x-y N, inclusive of x=0, y=0, and x=y=0, and a p-layer of p-type nitrogen-Group III compound semiconductor satisfying the formula Al_x Ga_y In_1-x-y N, inclusive of x=0, y=0, and x=y=0, said two n-layers having different electron concentrations from each other.

10. The semiconductor of claim 2, wherein said at least two sides of said sapphire substrate are opposing sides of said sapphire substrate.