Method of fabricating thin film semiconductor integrated circuit

• US 5,620,905 A
• Filed: 03/29/1995
• Issued: 04/15/1997
• Est. Priority Date: 10/20/1993
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Konuma, Toshimitsu, Hiroki, Masaaki, Takemura, Yasuhiko, Yamamoto, Mutsuo, Zhang, Hongyong
• Primary Examiner(s): Bowers, Jr., Charles L.
• Assistant Examiner(s): Radomsky, Leon
• Application Number:
  US08/413,104
• Time in Patent Office: 748 Days
• Field of Search: 437/44, 437/236, 437/237, 437/979, 437/983, 437/21, 437/101, 437/909, 437/40 TFT, 437/41 TFT, 148/DIG. 163, 257/900, 257/61, 257/59, 257/66, 257/69, 257/72
• US Class Current: 438/163
• CPC Class Codes: H01L 21/02422 Non-crystalline insulating materials, e.g. glass, polymers
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02686 Pulsed laser beam
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1285 using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: Y10S 438/981 Utilizing varying dielectric thickness

Abstract

In a semiconductor integrated circuit, a plurality of thin film transistors (TFTs) are formed on the same substrate having an insulating surface. Since gate electrodes formed in the TFTs are electrically insulated each other, voltages are applied independently to gate electrodes in an electrolytic solution during an anodization, to form an anodic oxide in at least both sides of each gate electrode. A thickness of the anodic oxide is changed in accordance with characteristics of the TFT. A width of high resistance regions formed in an active layer of each TFT is changed by ion doping using the anodic oxide having a desired thickness as a mask.

Claims

1. A method for producing a semiconductor device comprising the steps of:

forming first and second semiconductor regions on an insulating surface;

forming an insulating film on the semiconductor regions;

forming gate electrodes on the semiconductor regions respectively through the insulating film;

forming a porous anodic oxide on both sides of the gate electrode provided on only the first semiconductor region; and

forming barrier anodic oxides having same thickness on at least both sides of the gate electrodes provided on the first and second semiconductor regions; and

introducing impurity into the first and second semiconductor regions using the gate electrodes and the porous anodic oxide and the barrier anodic oxides as masks, to form offset regions in the first and second semiconductor regions of different widths between the first semiconductor region and the second semiconductor region.

2. The method of claim 1 wherein said porous anodic oxide is formed by anodic oxidation in an acidic electrolyte.

3. The method of claim 1 wherein said barrier anodic oxides are formed by anodic oxidation in a substantially neutral electrolyte.

4. The method of claim 1 wherein said barrier anodic oxides are more dense than said porous anodic oxide.

5. A method for producing a semiconductor device comprising the steps of:

forming a first semiconductor region on an insulating substrate in a pixel region;

forming a second semiconductor region on the insulating substrate in a peripheral circuit region;

forming an insulating film on the first and second semiconductor regions;

forming gate electrodes on the first and second semiconductor regions respectively through the insulating film;

forming a porous anodic oxide on at least both sides of the gate electrode provided only on the first semiconductor region;

forming barrier anodic oxides on at least both sides of the gate electrodes provided on the first and second semiconductor regions;

introducing impurity into the first and second semiconductor regions using the gate electrodes and the porous anodic oxide and the barrier anodic oxides as masks, to form offset regions in the first and second semiconductor regions of different widths between the first semiconductor region and the second semiconductor region,

wherein the offset regions formed in the first semiconductor region have the same width on both sides, and the offset regions formed in the second semiconductor region have the same width on both sides.

6. A method for producing a semiconductor device comprising the steps of:

forming first and second semiconductor regions on an insulating surface;

forming an insulating film on the semiconductor regions

forming gate electrodes on the semiconductor regions respectively through the insulating film;

forming porous anodic oxides having different thicknesses on both sides of the gate electrodes provided on the first and second semiconductor regions; and

forming a barrier anodic oxide on at least the both sides of the gate electrode provided on only the second semiconductor region;

etching a portion of the insulating film using the porous anodic oxides and the barrier anodic oxide and the gate electrodes as masks to pattern the insulating film into two islands;

removing the porous anodic oxides by etching; and

introducing impurity into the first and second semiconductor regions using the gate electrodes and the two islands and the barrier anodic oxide as masks, to form lightly doped regions in the first and second semiconductor regions of different widths between the first semiconductor region and the second semiconductor region, and to form an offset region in only the second semiconductor region.