Method for bypassing null-code sections for read-only memory by access line control

• US 5,620,915 A
• Filed: 07/12/1995
• Issued: 04/15/1997
• Est. Priority Date: 07/12/1995
• Status: Expired due to Term

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chen, Hsin-Li, Wu, Te-Sun
• Primary Examiner(s): TSAI, H JEY
• Application Number:
  US08/501,659
• Time in Patent Office: 643 Days
• Field of Search: 437/52, 437/48, 437/8, 365/189.01-189.07, 364/965.5
• US Class Current: 438/278
• CPC Class Codes: G11C 17/126 Virtual ground arrays

Abstract

The ROM device comprises a number of memory cells each is constructed based on a MOS transistor, the memory cells in the ROM are arranged into a number of rows and a columns. A number of word lines each connects to the gates of each of the MOS transistors of all the memory cells in each of the rows. A number of bit lines each connects to one of the source/drain pair of each of the MOS transistors of all the memory cells in each of the columns. A multiplexer comprises a number of transmitting transistors, each of the transmitting transistors is connected to a corresponding one of the bit lines, forming a current flow path including the transmitting transistor, the connected bit line, and the memory cells correspondingly connected to the bit line. A sense amplifier is coupled to the multiplexer for sensing the current flowing therethrough the current flow path to output a corresponding sense output signal. The method for bypassing null-code sections to comprise programing the transmitting transistor in the current flow path into an off status when all memory cells in the column connecting to the bit line of the transmitting transistor is required to contain null code.

Claims

1. A method for bypassing null-code sections in semiconductor read-only memory, the read-only memory having:

a plurality of memory cells each comprising a MOS transistor, the memory cells being arranged in a plurality of rows and a plurality of columns;

a plurality of word lines each connecting the gates of each of the MOS transistors of all the memory cells in each of the rows;

a plurality of bit lines each connecting one of the source/drain pair of each of the MOS transistors of all the memory cells in each of the columns;

a multiplexer means comprising a plurality of transmitting transistors, each of the transmitting transistors being connected to a corresponding one of the bit lines, forming a current flow path including the transmitting transistor, the connected bit line, and the memory cells correspondingly connected to the bit line; and

a sense amplifier means coupled to the multiplexer for sensing the current flowing therethrough the current flow path to output a corresponding sense output signal;

the method comprising;

programming the transmitting transistor in the current flow path into an off status when all memory cells in the column connecting to the bit line of the transmitting transistor is required to contain null code.

2. The method of claim 1, wherein the programming step comprises the step of programming the transmitting transistor into the off status simultaneously with all of the memory cells during a programming phase of fabrication of the read-only memory.

3. The method of claim 2, wherein the programming step comprises the step of photo-masked programming.

4. The method of claim 2, further comprising the step of selectively inverting the output of the sense amplifier means.

5. The method of claim 3, further comprising the step of selectively inverting the output of the sense amplifier means.

6. A method for bypassing null-code sections in semiconductor read-only memory, the read-only memory having:

a plurality of memory cells each comprising a MOS transistor, the memory cells being arranged in a plurality of rows and a plurality of columns, and a selected number of the rows of memory cells being further grouped into banks of memory-cell rows;

a plurality of bank-selecting transistors each connecting to a corresponding bank of memory cells;

a plurality of bank-selecting word lines each connecting the gates of each of the MOS transistors of all the memory cells in each of the banks;

a plurality of word lines each connecting the gates of each of the MOS transistors of all the memory cells in each of the rows;

a plurality of local bit lines each connecting one of the source/drain pair of each of the MOS transistors of all the memory cells in each of the banks;

a plurality of main bit lines each connecting a corresponding one of the bank-selecting transistors to a corresponding one of the local bit lines;

a multiplexer means comprising a plurality of transmitting transistors, each of the transmitting transistors being connected to a corresponding one of the main bit lines, forming a current flow path including the transmitting transistor, the connected main bit line, and the bank of memory cells correspondingly connected to the main bit line; and

a sense amplifier means coupled to the multiplexer for sensing the current flowing therethrough the current flow path to output a corresponding sense output signal;

the method comprising programming one of the bank-selecting transistors in the current flow path into an off status when all memory cells in the column connecting to the main bit line of the transmitting transistor is required to contain null code.

7. The method of claim 6, wherein the programming step comprises the step of programming the transmitting transistor into the off status simultaneously with all of the memory cells during a programming phase of fabrication of the read-only memory.

8. The method of claim 7, wherein the programming step comprises the step of photo-masked programming.

9. The method of claim 7, further comprising the step of selectively inverting the output of the sense amplifier means.

10. The method of claim 8, further comprising the step of selectively inverting the output of the sense amplifier means.

13. The method of claim 10, wherein the programming step comprises the step of photo-masked programming.

11. A method for bypassing null-code sections in semiconductor read-only memory, the read-only memory having:

a plurality of memory cells each comprising a MOS transistor, the memory cells being arranged in a plurality of rows and a plurality of columns, and a selected number of the rows of memory cells being further grouped into banks of memory-cell rows;

a plurality of bank-selecting transistors each connecting to a corresponding bank of memory cells;

a plurality of bank-selecting word lines each connecting the gates of each of the MOS transistors of all the memory cells in each of the banks;

a plurality of word lines each connecting the gates of each of the MOS transistors of all the memory cells in each of the rows;

a plurality of local bit lines each connecting one of the source/drain pair of each of the MOS transistors of all the memory cells in each of the banks;

a plurality of main bit lines each connecting a corresponding one of the bank-selecting transistors to a corresponding one of the local bit lines;

a multiplexer means comprising a plurality of transmitting transistors, each of the transmitting transistors being connected to a corresponding one of the main bit lines, forming a current flow path including the transmitting transistor, the connected main bit line, and the bank of memory cells correspondingly connected to the main bit line; and

a sense amplifier means coupled to the multiplexer for sensing the current flowing therethrough the current flow path to output a corresponding sense output signal;

the method comprising;

programming one of the transmitting transistors in the current flow path into an off status when all memory cells in the column connecting to the main bit line of the transmitting transistor is required to contain null code.

12. The method of claim 11, wherein the programming step comprises the step of programming the transmitting transistor into the off status simultaneously with all of the memory cells during the programming phase of the fabrication of the read-only memory.

14. The method of claim 12, further comprising the step of selectively inverting the output of the sense amplifier means.

15. The method of claim 14, further comprising the step of selectively inverting the output of the sense amplifier means.