Electrically programmable read-only memory cell

• US 5,621,233 A
• Filed: 06/05/1995
• Issued: 04/15/1997
• Est. Priority Date: 09/16/1994
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Woo, Michael P., Sharma, Umesh
• Primary Examiner(s): Ngo, Ngan V.
• Application Number:
  US08/462,410
• Time in Patent Office: 680 Days
• Field of Search: 257/314, 257/315, 257/316, 257/317, 257/318, 257/319, 257/320, 257/321, 257/322, 257/326, 257/371, 257/390, 365/185
• US Class Current: 257/316
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

EPROM cells include T-shaped floating gates (61, 171) and control gates that surround virtually all of the floating gates (61, 171) except for the portion of the floating gates (61, 171) that lie on a gate dielectric layer (51, 151). The EPROM cells may include customized well regions (22, 122) to allow flash erasing or individual cell erasing for electrically erasable EPROMs. Many different configurations of the memory cells are possible. The configurations of the source regions, drain regions, and well regions (22, 122) may be determined by how a user of the memory cells wants to program or erase the memory cells.

Claims

1. A semiconductor device including an array of electrically programmable read-only memory cells comprising:

a semiconductor substrate having a first conductivity type;

a first well region having a second conductivity type that is opposite the first conductivity type, wherein the first well region lies within the substrate;

a second well region having the first conductivity type, wherein the second well region lies within the first well region;

a third well region having the first conductivity type, wherein the third well region lies within the first well region and is spaced apart from the second well region;

a first plurality of floating gates overlying the first well region, wherein;

the first plurality of floating gates includes a second plurality of floating gates and a third plurality of floating gates;

the second plurality of floating gates overlie the second well region; and

the third plurality of floating gates overlie the third well region;

an intergate dielectric layer lying adjacent to the first plurality of floating gates; and

a first word line and a second word line lying adjacent to the intergate dielectric layer and overlying the first well region.

2. The semiconductor device of claim 1, wherein:

the first and second word lines have lengths that extend in a first direction;

the second and third well regions have lengths that extend in a second direction that is perpendicular to the first direction; and

each of the first and second word lines overlies the second and third well regions.

3. The semiconductor device of claim 1, wherein:

each of the floating gates has a T-shape that includes a trunk portion and a cross-bar portion;

the intergate dielectric layer has a uniform thickness along surfaces of the trunk and cross-bar portions of the floating gates; and

portions of the word lines underlie portions of the floating gates.

4. The semiconductor device of claim 1, wherein the intergate dielectric layer includes oxide-nitride-oxide and has an electrically measured oxide equivalent thickness in a range of 50-300 angstroms.