Chopped hall sensor with synchronously chopped sample-and-hold circuit

• US 5,621,319 A
• Filed: 12/08/1995
• Issued: 04/15/1997
• Est. Priority Date: 12/08/1995
• Status: Expired due to Term

• Current Assignee: Allegro Microsystems Incorporated (Sanken Electric Company Limited)
• Original Assignee: Allegro Microsystems Incorporated (Sanken Electric Company Limited)
• Inventors: Monreal, Gerardo, Bilotti, Alberto
• Primary Examiner(s): Strecker, Gerard R.
• Application Number:
  US08/569,814
• Time in Patent Office: 494 Days
• Field of Search: 324/207.12, 324/207.2, 324/225, 324/251, 324/117 H, 327/291, 327/310, 327/384-386, 327/510, 327/511, 327/551, 73/DIG. 3, 326/26
• US Class Current: 324/251
• CPC Class Codes: G01R 33/07 Hall effect devices

Abstract

A chopped Hall sensor includes a Hall-element switching circuit of the kind in which a Hall element has two pairs of diagonally opposite Hall contacts which are alternately connected to a pair of DC supply conductors and to a pair of Hall-stitching-circuit output conductors for alternately, during phase φ1 and nφ1 of a first clock signal, switching the Hall exciting current from flow in one to another direction through the Hall element. A linear analog double-differential Hall-voltage amplifier has an input connected to the output of the Hall switching-circuit. A sample-and-hold circuit is comprised of first and second elemental sample-and-hold circuits (ESHCs) with inputs connected respectively to the two Hall-voltage differential-amplifier outputs. The first and second ESHCs are respectively clocked, by second and third clock signals, to the sample Hall voltage signal only during phases φ2 and φ3 and to hold the sample signal during phases nφ2 and nφ3 respectively, where φ2 and φ3 occur respectively during a mid portion of phases φ1 and nφ1. Two inputs of a summer circuit are connected respectively to the outputs of the first and second ESHCs. A third and fourth ESHC may be added to form a crossed-polarity full-differential sample-and-hold circuit. The Hall voltage amplifier may include a clocked noise blanking circuit for reducing the differential-gain of the amplifier only during a time span encompassing each phase transition in the first clock signal.

Claims

1. A chopped Hall sensor of the kind including a Hall element having two pairs of diagonally opposed Hall contacts, said contacts being spaced-apart and located near the periphery of said Hall element, a pair of DC supply conductors to which a DC source for exciting said Hall-element may be connected, one clock signal generator for generating at a first clock output a binary clock signal ck1 having binary phases φ

1 and nφ

1, and a Hall-element switching-circuit means connected to said first clock output and having a pair of Hall switching-circuit output conductors for during phase φ

1 connecting one of said diagonally-opposed contact pairs to said pair of DC supply conductors while simultaneously connecting the other of said diagonally opposed contact pairs to said pair of Hall switching-circuit output conductors, and for during phase nφ

1 connecting said other of said diagonally-opposed contact pairs to said pair of DC supply conductors While simultaneously connecting said one pair of diagonally opposed Hall contacts to said pair of Hall switching-circuit output conductors, wherein the improvement comprises;

a) a companion clock signal generator connected to said one clock signal generator having a second clock output for generating at said second clock output a binary clock signal ck2 having a binary phase φ

2 occurring during a middle portion of each φ

1 phase of said ck1 signal, and having a third clock output for generating a binary clock at said third clock output a signal ck3 having a binary phase φ

3 occurring during a middle portion of each nφ

1 phase of said ck1 signal;

b) a linear analog double-differential Hall-voltage amplifier having a differential input connected to said pair of Hall switching-circuit output conductors;

c) a chopped sample-and-hold circuit comprised of first and second elemental sample-and-hold circuits, each of said first and second elemental sample and hold circuits having an input connected respectively to the one and another polarities of the differential output of said Hall-voltage amplifier, each of said first and second elemental sample and hold circuits having a sampling-enabling switch means connected respectively to said second and third clock outputs for respectively sampling the elemental sample and hold circuit input signals only during phases φ

2 and φ

3 and holding the sample signals at the respective outputs of said first and second elemental sample and hold circuits during phases nφ

2 and nφ

3 respectively; and

d) a summer circuit having a first input connected to the output of said first elemental sample and hold circuit and having a second input connected to the output of said second elemental sample and hold circuit, the output of said summer circuit serving as the output of said Hall sensor.

2. The chopped Hall sensor of claim 1 wherein said companion clock signal generator is additionally for generating at a fourth clock output a binary clock signal ck4 having a binary phase φ

4 that is synchronized to occur for a time span encompassing each occurrence of a transition between phases φ

1 and nφ

1 in the clock signal ck1, said double-differential Hall-voltage amplifier including an electrically actuated gain-reduction switch means connected to said fourth clock output for during each phase φ

4 in clock signal ck4 reducing the differential gain of said Hall-voltage amplifier.

3. The chopped Hall sensor of claim 1 wherein said chopped sample-and-hold circuit is additionally comprised of third and fourth elemental sample-and-hold circuits, each of said third and fourth elemental sample and hold circuits having an input connected respectively to said another and said one of the differential outputs of said Hall-voltage amplifier, each of said third and fourth elemental sample and hold circuits having a sampling-enabling switch means connected respectively to said second and third clock outputs for respectively sampling the elemental sample and hold circuit input signals only during phases φ

2 and φ

3 and holding the sample signals at the respective outputs of said third and fourth elemental sample and hold circuits during phases nφ

2 and nφ

3 respectively, said summer circuit additionally having a third input connected to said output of said third elemental sample and hold circuit and having a fourth input connected to said output of said fourth elemental sample and hold circuit, so that said chopped sample-and-hold circuit is a full-differential crossed-polarity sample-and-hold circuit.