In-phase and quadrature sampling circuit

• US 5,621,345 A
• Filed: 04/07/1995
• Issued: 04/15/1997
• Est. Priority Date: 04/07/1995
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Grant, Norman D., Ferguson, Paul F. Jr., Lee, Wai L.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): TON, MY TRANG
• Application Number:
  US08/418,546
• Time in Patent Office: 739 Days
• Field of Search: 327/552, 327/555, 327/557, 327/558, 327/559, 327/91, 327/254, 364/724.01, 364/724.1, 341/143, 341/155, 341/115, 375/27, 375/28, 375/39, 375/103, 375/244, 375/247, 375/261, 375/350, 375/298
• US Class Current: 327/254
• CPC Class Codes: H03D 7/165 at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002

Abstract

A circuit that provides samples of in-phase and quadrature components of an input waveform includes an oversampling ADC that receives the input waveform and converts the input waveform to digital samples at an oversampling rate. A first digital filter, coupled to the ADC, receives the digital samples from the ADC and provides the in-phase component samples of the input waveform. A second digital filter, coupled to the ADC, receives the digital samples from the ADC and provides the quadrature component samples of the input waveform.

Claims

1. A circuit that provides samples of in-phase and quadrature components of an input waveform comprising:

an oversampling ADC that receives the input waveform and converts the input waveform to digital samples having an input frequency at an oversampling rate;

a first digital decimation filter, coupled to the ADC, that receives the digital samples from the ADC and provides the in-phase component samples having a center frequency different from the input frequency; and

a second digital decimation filter, coupled to the ADC, that receives the digital samples from the ADC and provides the quadrature component samples having a center frequency different from the input frequency.

2. The circuit as claimed in claim 1 wherein the oversampling ADC includes a sigma-delta ADC.

3. The circuit as claimed in claim 2 wherein the sigma-delta ADC includes a one-bit sigma-delta ADC.

4. The circuit as claimed in claim 1 wherein each of the first and second digital filters includes a multi-tap decimation/demodulation filter, and wherein the demodulation performed by the first filter is approximately 90 degrees out of phase with that of the second filter.

5. The circuit as claimed in claim 4 wherein the first digital filter includes multiple coefficients, at least one coefficient corresponding to each filter tap, each coefficient being equal to the product of a corresponding constant decimation filter coefficient value and a respective cosine wave sample value.

6. The circuit as claimed in claim 5 further including a memory element, coupled to the first digital filter, that stores a plurality of coefficients, at least two coefficients corresponding to each filter tap.

7. The circuit as claimed in claim 6 further including a processor, coupled to the memory element and the first digital filter, that dynamically computes the coefficients of the first digital filter.

8. The circuit as claimed in claim 4 wherein the second digital filter includes multiple coefficients, at least one coefficient corresponding to each filter tap, each coefficient being equal to the product of a corresponding constant decimation filter coefficient value and a respective sine wave sample value.

9. The circuit as claimed in claim 8 further including a memory element, coupled to the second digital filter, that stores a plurality of coefficients, at least two coefficients corresponding to each filter tap.

10. The circuit as claimed in claim 9 further including a processor, coupled to the memory element and the second digital filter, that dynamically computes the coefficients of the second digital filter.

11. The circuit as claimed in claim 4 wherein each of the digital filters includes a one-bit digital filter.

12. A method for providing in-phase and quadrature component samples of an input waveform comprising the steps of:

converting the input waveform to digital samples having an input frequency at an oversampling rate;

with a first digital decimation filter, providing, from the digital samples, the in-phase component samples having a center frequency different from the input frequency; and

with a second digital decimation filter, providing, from the digital samples, the quadrature component samples having a center frequency different from the input frequency.

13. A method as claimed in claim 12 wherein the step of converting includes the step of sigma-delta modulating the input waveform.

14. A method as claimed in claim 12 wherein the first step of providing includes the step of demodulating and decimating the digital samples.

15. A method as claimed in claim 12 wherein the second step of providing includes the step of demodulating and decimating the digital samples.

16. A circuit that provides in-phase and quadrature component samples of an input waveform comprising:

means for converting the input waveform to digital samples having an input frequency at an oversampling rate;

first decimation means, coupled directly to the means for converting, for providing from the digital samples the in-phase component samples having a center frequency different from the input frequency; and

second decimation means, coupled directly to the means for converting, for providing from the digital samples the quadrature component samples having a center frequency different from the input frequency.