Optimized processing of signals for enhanced cross-correlation in a satellite positioning system receiver

• US 5,621,416 A
• Filed: 06/16/1995
• Issued: 04/15/1997
• Est. Priority Date: 02/02/1995
• Status: Expired due to Term

• Current Assignee: Trimble Navigation Limited (Trimble Inc.)
• Original Assignee: Trimble Navigation Limited (Trimble Inc.)
• Inventors: Lennen, Gary R.
• Primary Examiner(s): Tarcza, Thomas H.
• Assistant Examiner(s): PHAN, DAO LINDA
• Application Number:
  US08/491,415
• Time in Patent Office: 669 Days
• Field of Search: 342/357, 342/352, 342/81, 455/12.1
• US Class Current: 342/357.68
• CPC Class Codes: G01S 19/32 Multimode operation in a single same satellite system, e.g. GPS L1/L2
• CPC Class Codes: G01S 19/33 Multimode operation in different systems which transmit time stamped messages, e.g. GPS/GLONASS

Abstract

The optimum SPS receiver is described that allows to optimize the demodulation of the unknown W-code generated by the Global Positioning System (GPS). The assumed timing and the spectrum structure of W-code are used for selecting the optimum digital filter that optimizes the signal-to-noise (STN) ratio of the received satellite signals.

Claims

1. A system for optimum correlation processing of L1 and L2 signals received from a SPS satellite by a SPS RECEIVER, said system comprising:

a RECEIVING MEANS for receiving a known C/A code modulated on L1 carrier frequency, for receiving an unknown Y code modulated on L1 carrier frequency signal, and for receiving an unknown Y code modulated on L2 carrier frequency signal from at least one satellite;

wherein said received L1 , and L2 signals contain propagation noise; and

wherein said Y code comprises a known P code and an unknown W code; and

at least one DIGITAL CHANNEL PROCESSING MEANS for;

(1) locally generating replica of said C/A code modulated on L1 carrier frequency signal;

(2) locally generating replica of said P code modulated on L1 carrier frequency signal, wherein said locally generated replica of L1 signal do not contain propagation noise;

(3) extracting of an estimate of said Y code from said L1 signal, and from said L2 signal, wherein said estimate signals contain propagation noise;

(4) correlating a locally generated replica of C/A code with the received L1 code for obtaining an estimate of L1 group delay (L1 pseudo-range) and L1 carrier phase;

(5) removing said P code from said locally extracted estimate of said L1 Y code to obtain a locally extracted estimate of said L1 W code;

(6) removing said P code from said locally extracted estimate of said L2 Y code to obtain a locally extracted estimate of said L2 W code; and

(7) correlating said locally extracted estimate of said L1 W code with said locally extracted estimate of said L2 W code to obtain relative offset in group delay between L1 and L2 signals and for obtaining an independent estimate of L2 carrier phase; and

wherein said RECEIVING MEANS further comprises;

a dual frequency patch ANTENNA MEANS for receiving said L1 and L2 satellite signals;

a FILTER/LNA MEANS conductively connected to said ANTENNA MEANS for performing filtering and low noise amplification of said L1 and L2 signals, wherein said FILTER/LNA determines the noise/signal ratio of the received signals L1 and L2;

a DOWNCONVERTER MEANS conductively connected to said FILTER/LNA MEANS for mixing and converting said L1 and L2 signals; and

an IF PROCESSOR MEANS conductively connected to said DOWNCONVERTER MEANS for transforming, said converted L1 and L2 signals into digitally sampled quadrature versions of L1 and L2 signals (IL1 , QL1 , IL2 , QL2 );

a MASTER OSCILLATOR MEANS; and

a FREQUENCY SYNTHESIZER MEANS conductively connected to said MASTER OSCILLATOR MEANS, to said IF PROCESSOR MEANS, to said DOWNCONVERTER MEANS, and to at least one said DIGITAL, CHANNEL PROCESSING MEANS, wherein said FREQUENCY SYNTHESIZER MEANS generates several timing signals; and

wherein said IF PROCESSOR MEANS further comprises;

a first POWER SPLITTER MEANS connected to said DOWNCONVERTER MEANS and to said FREQUENCY SYNTHESIZER MEANS for power splitting said L1 signal into two signals;

a second POWER SPLITTER MEANS connected to said DOWNCONVERTER MEANS and to said FREQUENCY SYNTHESIZER MEANS for power splitting said L2 signal into two signals;

a first MULTIPLIER MEANS for multiplying said L1 signal with an inphase (I) version of said second LO2 signal to produce an IL1 signal;

a second MULTIPLIER MEANS for multiplying said L1 signal with a quadrature (Q) version of said second LO2 signal to produce a QL1 signal;

a third MULTIPLIER MEANS for multiplying said L2 signal with an inphase (I) version of said 2-nd LO2 signal to produce an IL2 signal

a fourth MULTIPLIER MEANS for multiplying said L2 signal with a quadrature (Q) version of said 2-nd LO2 signal to produce a QL2 signal;

a first AMPLIFIER MEANS connected to said first MULTIPLIER MEANS for amplifying said IL1 signal;

a second AMPLIFIER MEANS connected to said second MULTIPLIER MEANS for amplifying said QL1 signal;

a third AMPLIFIER MEANS connected to said third MULTIPLIER MEANS for amplifying said IL2 signal;

a fourth AMPLIFIER MEANS connected to said fourth MULTIPLIER MEANS for amplifying said QL2 signal;

a first one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said first AMPLIFIER MEANS for performing 1-bit quantization operation on said IL1 signal;

a second one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said second AMPLIFIER MEANS for performing 1-bit quantization operation on said QL1 signal;

a third one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said third AMPLIFIER MEANS for performing 1-bit quantization operation on said IL2 signal;

a fourth one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said fourth AMPLIFIER MEANS for performing 1-bit quantization operation on said QL2 signal;

a first FLIP-FLOP MEANS (FF1) connected to said first one-bit A/D CONVERTER for sampling said IL1 signal, wherein said sampling operation is performed by clocking said IL1 signal through said FF1at sampling clock (SCLK) rate;

a second FLIP-FLOP MEANS (FF2) connected to said second one-bit A/D CONVERTER for sampling said QL1 signal, wherein said sampling operation is performed by clocking said QL1 signal through said FF2at sampling clock (SCLK) rate;

a third FLIP-FLOP MEANS (FF3) connected to said third one-bit A/D CONVERTER for sampling said IL2 signal, wherein said sampling operation is performed by clocking said IL2 signal through said FF3 at sampling clock SCLK) rate; and

a fourth FLIP-FLOP MEANS (FF4) connected to said fourth one-bit A/D CONVERTER for sampling said QL2 signal, wherein said sampling operation is performed by clocking said QL2 signal through said FF4 at sampling clock (SCLK) rate; and

wherein each said DIGITAL CHANNEL PROCESSING MEANS further comprises;

an L1 TRACKER MEANS for tracking L1 C/A code when Y code is ON and for tracking L1 P code when Y code is OFF;

an L2 TRACKER MEANS connected to said L1 TRACKER MEANS for tracking an enhanced cross correlated W code when Y code is ON and for tracking L2 P code when Y code is OFF; and

a MICROPROCESSOR MEANS system connected to said L1 TRACKER MEANS and to said L2 TRACKER MEANS;

wherein said L1 TRACKER MEANS is fed by digitized inphase IL1 and quadrature QL1 of L1 signal outputted by said IF PROCESSOR MEANS; and

wherein said L2 TRACKER MEANS is fed by digitized inphase I L2 and quadrature QL2 of L2 signal outputted by said IF PROCESSOR MEANS; and

wherein each said L1 and L2 TRACKER MEANS are synchronously clocked by said SCLK signal and synchronously referenced by said MSEC signal to local reference time;

said SCLK and MSEC signals being outputted by said FREQUENCY SYNTHESIZER MEANS; and

wherein said L2 TRACKER MEANS when Y code is ON is fed from said L1 TRACKER MEANS by generated by said L1 TRACKER MEANS three signals;

L1 P code, filtered estimate of L1 W code, and C/A code epoch (EP code); and

wherein said MICROPROCESSOR MEANS system is fed by output signals from said L1 TRACKER MEANS and said L2 TRACKER MEANS; and

wherein said L1 TRACKER MEANS and said L2 TRACKER MEANS are fed by control signal from said MICROPROCESSOR MEANS; and

wherein said L1 TRACKER MEANS further comprises;

a CODE GENERATOR MEANS for providing a locally generated replica of C/A code and P code;

a MULTIPLEXER MEANS 1 connected to said CODE GENERATOR MEANS for selecting a locally generated code C/A when Y code is ON and for selecting a locally generated P code when Y code is OFF, said MULTIPLEXER MEANS 1 being controlled by said MICROPROCESSOR MEANS system;

a carrier numerically controlled oscillator (CARRIER NCO MEANS

     1) connected to said MULTIPLEXER MEANS 1;

a CARRIER MIXER MEANS 1 connected to said CARRIER NCO MEANS 1 for multiplying outputted by said IF PROCESSOR MEANS digitized inphase IL1 and Q L1 signals having carrier frequency with outputted by said CARRIER NCO MEANS 1 inphase and quadrature components of digital carrier;

wherein said CARRIER MIXER MEANS 1 outputs inphase IL1 and quadrature Q L1 signals having zero carrier frequency;

a CODE MIXER MEANS 1 connected to said CARRIER MIXER MEANS 1, connected to said CODE GENERATOR MEANS and connected to said CARRIER NCO MEANS 1 for code correlating said CARRIER MIXER MEANS 1 output signals with said locally generated replica of C/A code;

wherein when said L1 TRACKER MEANS'"'"'s carrier tracking loop is closed via said CARRIER NCO MEANS 1 the input to said CODE MIXER MEANS 1 represents the satellite signal L1 C/A code; and

wherein said CODE MIXER MEANS 1 performs said code correlation at 3 time points (early, punctual and late) on the autocorrelation function graph creating an early, a punctual and a late sample of the autocorrelation function;

a block CORRELATORS MEANS 1 connected to said CODE MIXER MEANS 1 for integrating said early, punctual and late samples of said autocorrelation function;

wherein said CORRELATORS MEANS 1 output signal is fed to said MICROPROCESSOR MEANS system at a rate of L1 C/A code epoch, and wherein said MICROPROCESSOR MEANS uses said CORRELATORS MEANS 1 output signal to develop feedback signals for the carrier tracking loop and for the code tracking loop;

a code numerically controlled oscillator (CODE NCO MEANS) connected to said block CORRELATORS MEANS 1 and connected to said CODE GENERATOR MEANS for providing a clocking signal at C/A code rate and for providing a clocking signal at P code rate, said C/A code clocking rate and said P code clocking rate driving said CODE GENERATOR MEANS;

said CODE NCO MEANS also providing a mechanism for aligning said locally generated replica of C/A code with said incoming satellite C/A code;

a CODE MIXER MEANS 2 connected to said CARRIER MIXER MEANS 1 and connected to said CODE GENERATOR MEANS, said CARRIER MIXER MEANS 1 outputting an estimate of L1 Y code as an input to said CODE MIXER MEANS 2, said CODE GENERATOR MEANS outputting said local replica of known L1 P code as input to said CODE MIXER MEANS 2, wherein said CODE MIXER MEANS 2 removes known L1 P code from said estimate of L1 Y code and outputs an estimate of L1 W code;

a DIGITAL DELAY MEANS 1 connected to said CODE MIXER MEANS 2 for delaying under said MICROPROCESSOR MEANS system control said L1 W code estimate;

a DIGITAL FILTER MEANS 1 connected to said DIGITAL DELAY MEANS 1 for reducing the bandwidth of said L1 W code estimate;

wherein said delayed and filtered L1 W code estimate is sent for processing to said L2 TRACKER MEANS;

a DIGITAL DELAY MEANS 2 connected to said CODE GENERATOR MEANS for delaying said P code output from said CODE GENERATOR MEANS, wherein said delayed P code is sent to said L2 TRACKER MEANS; and

a RESOLVER MEANS connected to said CARRIER NCO MEANS 1 for toggling the digital delay between the two delays in the DIGITAL DELAY 1 and in the DIGITAL DELAY 2, wherein the resulting delay is the average of the relative time spent on each said delay;

and wherein said L1 C/A code epoch (EP) is sent to said L2 TRACKER MEANS; and

wherein said DIGITAL FILTER MEANS 1 further comprises a finite impulse response (FIR) DIGITAL FILTER 1; and

wherein said FIR DIGITAL FILTER 1 performs the enhanced cross correlation operation by matching the observed W-code spectrum and by optimizing the signal-to-noise (STN) ratio of the cross-correlation process.

2. The system of claim 1, wherein said FIR DIGITAL FILTER 1 is implemented using a direct form transfer function.

3. The system of claim 1, wherein said FIR DIGITAL FILTER 1 is implemented using a cascade form transfer function.

4. The system of claim 1, wherein said FIR DIGITAL FILTER 1 is implemented using a parallel form transfer function.

9. The system of claim 1, wherein said FIR DIGITAL FILTER 1 further comprises

a first L-bit SHIFT REGISTER MEANS (X1 ,X2, . . . Xm), m being an integer, for making an m- number of delayed copies of an input signal X, wherein said input signal X comprises said I estimate of L2 W code, wherein a first copy of said input signal X1 is delayed by one sample clock SCLK, a second copy of said input signal X2 is delayed by two sample clocks, an (i) copy of said input signal X1 is delayed by (i) sample clocks, i being an integer, and an m-copy of said input signal Xm is delayed by (m) sample clocks;

an m-number of MULTIPLIER MEANS (C1, . . . Cm), wherein a first MULTIPLIER MEANS C1 transforms said X1 signal into a C1X1 signal; and

wherein a second MULTIPLIER MEANS C2transforms said X2 signal into a C2X2 signal, and wherein an (i) MULTIPLIER MEANS Ci transform said Xi signal into a CiXi signal, and wherein an (m) MULTIPLIER MEANS transforms said Xm signal into a CmXm signal;

and an ADDER MEANS connected to each of said Ci MULTIPLIER MEANS for adding each said CiXi signals into an output function Yout, wherein said output function Yout is equal to;

space="preserve" listing-type="equation">Yout=C1X1+C2X2+ . . . CmXm;

wherein said FIR DIGITAL FILTER MEANS 1 optimizes the signal-to-noise ratio by adapting to changes in the input signal X frequency spectrum.

14. The system of claim 2, wherein said FIR DIGITAL FILTER 2 is implemented using a parallel form transfer function.

5. A system for optimum correlation processing of L1 and L2 signals received from a SPS satellite by a SPS RECEIVER, said system comprising:

a RECEIVING MEANS for receiving a known C/A code modulated on L1 carrier frequency, for receiving an unknown Y code modulated on L1 carrier frequency signal, and for receiving an unknown Y code modulated on L2 carrier frequency signal from at least one satellite;

wherein said received L1 , and L2 signals contain propagation noise; and

wherein said Y code comprises a known P code and an unknown W code; and

at least one DIGITAL CHANNEL PROCESSING MEANS for;

(1) locally generating replica of said C/A code modulated on L1 carrier frequency signal;

(2) locally generating replica of said P code modulated on L1 carrier frequency signal, wherein said locally generated replica of L1 signal do not contain propagation noise;

(3) extracting of an estimate of said Y code from said L1 signal, and from said L2 signal, wherein said estimate signals contain propagation noise;

(4) correlating a locally generated replica of C/A code with the received L1 code for obtaining an estimate of L1 group delay (L1 pseudo-range) and L1 carrier phase;

(5) removing said P code from said locally extracted estimate of said L1 Y code to obtain a locally extracted estimate of said L1 W code;

(6) removing said P code from said locally extracted estimate of said L2 Y code to obtain a locally extracted estimate of said L2 W code; and

(7) correlating said locally extracted estimate of said L1 W code with said locally extracted estimate of said L2 W code to obtain relative offset in group delay between L1 and L2 signals and for obtaining an independent estimate of L2 carrier phase; and

wherein said RECEIVING MEANS further comprises;

a dual frequency patch ANTENNA MEANS for receiving said L1 and L2 satellite signals;

a FILTER/LNA MEANS conductively connected to said ANTENNA MEANS for performing filtering and low noise amplification of said L1 and L2 signals, wherein said FILTER/LNA determines the noise/signal ratio of the received signals L1 and L2;

a DOWNCONVERTER MEANS conductively connected to said FILTER/LNA MEANS for mixing and converting said L1 and L2 signals; and

an IF PROCESSOR MEANS conductively connected to said DOWNCONVERTER MEANS for transforming said converted L1 and L2 signals into digitally sampled quadrature versions of L1 and L2 signals (IL1 , QL1 , IL2 , QL2 );

a MASTER OSCILLATOR MEANS; and

a FREQUENCY SYNTHESIZER MEANS conductively connected to said MASTER OSCILLATOR MEANS, to said IF PROCESSOR MEANS, to said DOWNCONVERTER MEANS, and to at least one said DIGITAL, CHANNEL PROCESSING MEANS, wherein said FREQUENCY SYNTHESIZER MEANS generates several timing signals; and

wherein said IF PROCESSOR MEANS further comprises;

a first POWER SPLITTER MEANS connected to said DOWNCONVERTER MEANS and to said FREQUENCY SYNTHESIZER MEANS for power splitting said L1 signal into two signals;

a second POWER SPLITTER MEANS connected to said DOWNCONVERTER MEANS and to said FREQUENCY SYNTHESIZER MEANS power splitting said L2 signal into two signals;

a first MULTIPLIER MEANS for multiplying said L1 signal with an inphase (I) version of said 2-nd LO2 signal to produce an IL1 signal;

a second MULTIPLIER MEANS for multiplying said L1 signal with a quadrature (Q) version of said 2-nd LO2 signal to produce a QL1 signal;

a third MULTIPLIER MEANS for multiplying said L2 signal with an inphase (I) version of said 2-nd LO2 signal to produce an IL2 signal;

a fourth MULTIPLIER MEANS for multiplying said L2 signal with a quadrature (Q) version of said 2-nd LO2 signal to produce a QL2 signal;

a first AMPLIFIER MEANS connected to said first MULTIPLIER MEANS for amplifying said IL1 signal;

a second AMPLIFIER MEANS connected to said second MULTIPLIER MEANS for amplifying said QL1 signal;

a third AMPLIFLER MEANS connected to said third MULTIPLIER MEANS for amplifying said IL2 signal;

a fourth AMPLIFIER MEANS connected to said fourth MULTIPLIER MEANS, for amplifying said QL2 signal;

a first one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said first AMPLIFIER MEANS for performing 1-bit quantization operation on said IL1 signal;

a second one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said second AMPLIFIER MEANS for performing 1-bit quantization operation on said QL1 signal;

a third one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said third AMPLIFIER MEANS for performing 1-bit quantization operation on said IL2 signal;

a fourth one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said fourth AMPLIFIER MEANS for performing 1-bit quantization operation on said QL2 signal;

a first FLIP-FLOP MEANS (FF1) connected to said first one-bit A/D CONVERTER for sampling said IL1 signal, wherein said sampling operation is performed by clocking said IL1 signal through said FF1 at sampling clock (SCLK) rate;

a second FLIP-FLOP MEANS (FF2) connected to said second one-bit A/D CONVERTER for sampling said QL1 signal, wherein said sampling operation is performed by clocking said QL1 signal through said FF2 at sampling clock (SCLK) rate;

a third FLIP-FLOP MEANS (FF3) connected to said third one-bit A/D CONVERTER for sampling said IL2 signal, wherein said sampling operation is performed by clocking said IL2 signal through said FF3 at sampling clock (SCLK)rate; and

a fourth FLIP-FLOP MEANS (FF4) connected to said fourth one-bit A/D CONVERTER for sampling said QL2 signal, wherein said sampling operation is performed by clocking said QL2 signal through said FF4 at sampling clock (SCLK) rate; and

wherein each said DIGITAL CHANNEL PROCESSING MEANS further comprises;

an L1 TRACKER MEANS for tracking L1 C/A code when Y code is ON and for tracking L1 P code when Y code is OFF;

an L2 TRACKER MEANS connected to said L1 TRACKER MEANS for tracking an enhanced cross correlated W code when Y code is ON and for tracking L2 P code when Y code is OFF; and

a MICROPROCESSOR MEANS system connected to said L1 TRACKER MEANS and to said L2 TRACKER MEANS;

wherein said L1 TRACKER MEANS is fed by digitized inphase IL1 and quadrature QL1 of L1 signal outputted by said IF PROCESSOR MEANS; and

wherein said L2 TRACKER MEANS is fed by digitized inphase I L2 and quadrature QL2 of L2 signal outputted by said IF PROCESSOR MEANS; and

wherein each said L1 and L2 TRACKER MEANS are synchronously clocked by said SCLK signal and synchronously referenced by said MSEC signal to local reference time;

said SCLK and MSEC signals being outputted by said FREQUENCY SYNTHESIZER MEANS; and

wherein said L2 TRACKER MEANS when Y code is ON is fed from said L1 TRACKER MEANS by generated by said L1 TRACKER MEANS three signals;

L1 P code, filtered estimate of L1 W code, and C/A code epoch (EP code); and

wherein said MICROPROCESSOR MEANS system is fed by output signals from said L1 TRACKER MEANS and said L2 TRACKER MEANS; and

wherein said L1 TRACKER MEANS and said L2 TRACKER MEANS are fed by control signal from said MICROPROCESSOR MEANS; and

wherein said L1 TRACKER MEANS further comprises;

a CODE GENERATOR MEANS for providing a locally generated replica of C/A code and P code;

a MULTIPLEXER MEANS 1 connected to said CODE GENERATOR MEANS for selecting a locally generated code C/A when Y code is ON and for selecting a locally generated P code when Y code is OFF, said MULTIPLEXER MEANS 1 being controlled by said MICROPROCESSOR MEANS system;

a carrier numerically controlled oscillator (CARRIER NCO MEANS

     1) connected to said MULTIPLEXER MEANS 1;

a CARRIER MIXER MEANS 1 connected to said CARRIER NCO MEANS 1 for multiplying outputted by said IF PROCESSOR MEANS digitized inphase IL1 and Q L1 signals having carrier frequency with outputted by said CARRIER NCO MEANS 1 inphase and quadrature components of digital carrier;

wherein said CARRIER MIXER MEANS 1 outputs inphase IL1 and quadrature Q L1 signals having zero carrier frequency;

a CODE MIXER MEANS 1 connected to said CARRIER MIXER MEANS 1, connected to said CODE GENERATOR MEANS and connected to said CARRIER NCO MEANS 1 for code correlating said CARRIER MIXER MEANS 1 output signals with said locally generated replica of C/A code;

wherein when said L1 TRACKER MEANS '"'"'s carrier tracking loop is closed via said CARRIER NCO MEANS 1 the input to said CODE MIXER MEANS 1 represents the satellite signal L1 C/A code; and

wherein said CODE MIXER MEANS 1 performs said code correlation at 3 time points (early, punctual and late) on the autocorrelation function graph creating an early, a punctual and a late sample of the autocorrelation function;

a block CORRELATORS MEANS 1 connected to said CODE MIXER MEANS 1 for integrating said early, punctual and late samples of said autocorrelation function;

wherein said CORRELATORS MEANS 1 output signal is fed to said MICROPROCESSOR MEANS system at a rate of L1 C/A code epoch, and wherein said MICROPROCESSOR MEANS uses said CORRELATORS MEANS 1 output signal to develop feedback signals for the carrier tracking loop and for the code tracking loop;

a code numerically controlled oscillator (CODE NCO MEANS) connected to said block CORRELATORS MEANS 1 and connected to said CODE GENERATOR MEANS for providing a clocking signal at C/A code rate and for providing a clocking signal at P code rate, said C/A code clocking rate and said P code clocking rate driving said CODE GENERATOR MEANS;

said CODE NCO MEANS also providing a mechanism for aligning said locally generated replica of C/A code with said incoming satellite C/A code;

a CODE MIXER MEANS 2 connected to said CARRIER MIXER MEANS 1 and connected to said CODE GENERATOR MEANS, said CARRIER MIXER MEANS 1 outputting an estimate of L1 Y code as an input to said CODE MIXER MEANS 2, said CODE GENERATOR MEANS outputting said local replica of known L1 P code as input to said CODE MIXER MEANS 2, wherein said CODE MIXER MEANS 2 removes known L1 P code from said estimate of L1 Y code and outputs an estimate of L1 W code;

a DIGITAL DELAY MEANS 1 connected to said CODE MIXER MEANS 2 for delaying under said MICROPROCESSOR MEANS system said control said L1 W code estimate;

a DIGITAL FILTER MEANS 1 connected to said DIGITAL DELAY MEANS 1 for reducing the bandwidth of said L1 W code estimate;

wherein said delayed and filtered L1 W code estimate is sent for processing to said L2 TRACKER MEANS;

a DIGITAL DELAY MEANS 2 connected to said CODE GENERATOR MEANS for delaying said P code output from said CODE GENERATOR MEANS, wherein said delayed P code is sent to said L2 TRACKER MEANS; and

a RESOLVER MEANS connected to said CARRIER NCO MEANS 1 for toggling the digital delay between the two delays in the DIGITAL DELAY 1 and in the DIGITAL DELAY 2, wherein the resulting delay is the average of the relative time spent on each said delay;

and wherein said L1 C/A code epoch (EP) is sent to said L2 TRACKER MEANS; and

wherein said DIGITAL FILTER MEANS 1 further comprises an infinite impulse response (IIR) DIGITAL FILTER 1; and

wherein said IIR DIGITAL FILTER 1 performs the enhanced cross correlation operation by matching the observed W-code spectrum and by optimizing the signal-to-noise (STN) ratio of the cross-correlation process.

6. The system of claim 5, wherein said IIR DIGITAL FILTER 1 is implemented using a direct form transfer function.

7. The system of claim 5, wherein said IIR DIGITAL FILTER 1 is implemented using a cascade form transfer function.

8. The system of claim 5, wherein said IIR DIGITAL FILTER 1 is implemented using a parallel form transfer function.

10. The system of claim 5, wherein said IIR DIGITAL FILTER 1 further comprises

a first L-bit SHIFT REGISTER MEANS (X1 ,X2, . . . Xm), m being an integer, for making an m- number of delayed copies of an input signal X, wherein a first copy of said input signal X1 is delayed by one sample clock SCLK, a second copy of said input signal X2 is delayed by two sample clocks, an (i) copy of said input signal Xi is delayed by (i) sample clocks, i being an integer, and an m-copy of said input signal Xm is delayed by (m) sample clocks;

an M-number of MULTIPLIER MEANS (C1, . . . Cm), wherein a first MULTIPLIER MEANS C1 transforms said X1 signal into a C1X1 signal; and

wherein a second MULTIPLIER MEANS C2transforms said X2 signal into a C2X2 signal, and wherein an (i) MULTIPLIER MEANS Ci transform said Xi signal into a CiXi signal, and wherein an (m) MULTIPLIER MEANS transforms said Xm signal into a CmXm signal;

a second L-bit SHIFT REGISTER MEANS (Y1,Y2 , . . . Yn), n being an integer, for making an n- number of delayed copies of an output signal Y, and wherein a first copy of said output signal Y1 is delayed by one sample clock SCLK, a second copy of said output signal Y2 is delayed by two sample clocks, an (i) copy of said output signal Yi is delayed by (i) sample clocks, i being an integer, and an n-copy of said output signal Yn is delayed by (n) sample clocks;

an n-number of MULTIPLIER MEANS (B1, . . . Bn), wherein a first MULTIPLIER MEANS B1 transforms said Y1 signal into a B1Y1 signal; and

wherein a second MULTIPLIER MEANS B2 transforms said Y2 signal into a B2Y2 signal, and wherein an (i) MULTIPLIER MEANS Bi transform said Yi signal into a BiYi signal, and wherein an (n) MULTIPLIER MEANS Bn transforms said Ym signal into a BnYn signal;

and an ADDER MEANS connected to each of said Ci and Bi MULTIPLIER MEANS for adding each said CiXi and BiYi signals into an output function Yout, wherein said output function Yout is equal to;

space="preserve" listing-type="equation">Yout=C1X1+C2X2+ . . . +CmXm+B1Y1+B2Y2+ . . . +BnYn;

and wherein said FIR DIGITAL FILTER MEANS 1 optimizes the signal-to-noise ratio by adapting to changes in the input signal X frequency spectrum.

11. A system for optimum correlation processing of L1 and L2 signals received from a SPS satellite by a SPS RECEIVER, said system comprising:

a RECEIVING MEANS for receiving a known C/A code modulated on L1 carrier frequency, for receiving an unknown Y code modulated on L1 carrier frequency signal, and for receiving an unknown Y code modulated on L2 carrier frequency signal from at least one satellite;

wherein said received L1 , and L2 signals contain propagation noise; and

wherein said Y code comprises a known P code and an unknown W code; and

at least one DIGITAL CHANNEL PROCESSING MEANS for;

(1) locally generating replica of said C/A code modulated on L1 carrier frequency signal;

(2) locally generating replica of said P code modulated on L1 carrier frequency signal, wherein said locally generated replica of L1 signal do not contain propagation noise;

(3) extracting of an estimate of said Y code from said L1 signal, and from said L2 signal, wherein said estimate signals contain propagation noise;

(4) correlating a locally generated replica of C/A code with the received L1 code for obtaining an estimate of L1 group delay (L1 pseudo-range) and L1 carrier phase;

(5) removing said P code from said locally extracted estimate of said L1 Y code to obtain a locally extracted estimate of said L1 W code;

(6) removing said P code from said locally extracted estimate of said L2 Y code to obtain a locally extracted estimate of said L2 W code; and

(7) correlating said locally extracted estimate of said L1 W code with said locally extracted estimate of said L2 W code to obtain relative offset in group delay between L1 and L2 signals and for obtaining an independent estimate of L2 carrier phase; and

wherein said RECEIVING MEANS further comprises;

a dual frequency patch ANTENNA MEANS for receiving said L1 and L2 satellite signals;

a FILTER/LNA MEANS conductively connected to said ANTENNA MEANS for performing filtering and low noise amplification of said L1 and L2 signals, wherein said FILTER/LNA determines the noise/signal ratio of the received signals L1 and L2;

a DOWNCONVERTER MEANS conductively connected to said FILTER/LNA MEANS for mixing and converting said L1 and L2 signals; and

an IF PROCESSOR MEANS conductively connected to said DOWNCONVERTER MEANS for transforming said converted L1 and L2 signals into digitally sampled quadrature versions of L1 and L2 signals (IL1 , QL1 , IL2 , QL2 );

a MASTER OSCILLATOR MEANS; and

a FREQUENCY SYNTHESIZER MEANS conductively connected to said MASTER OSCILLATOR MEANS, to said IF PROCESSOR MEANS, to said DOWNCONVERTER MEANS, and to at least one said DIGITAL, CHANNEL PROCESSING MEANS, wherein said FREQUENCY SYNTHESIZER MEANS generates several timing signals; and

wherein said IF PROCESSOR MEANS further comprises;

a first POWER SPLITTER MEANS connected to said DOWNCONVERTER MEANS and to said FREQUENCY SYNTHESIZER MEANS for power splitting said L1 signal into two signals;

a second POWER SPLITTER MEANS connected to said DOWNCONVERTER MEANS and to said FREQUENCY SYNTHESIZER MEANS for power splitting said L2 signal into two signals;

a first MULTIPLIER MEANS for multiplying said L1 signal with an inphase (I) version of said 2-nd LO2 signal to produce an IL1 signal;

a second MULTIPLIER MEANS for multiplying said L1 signal with a quadrature (Q) version of said 2-nd LO2 signal to produce a QL1 signal;

a third MULTIPLIER MEANS for multiplying said L2 signal with an inphase (I) version of said 2-nd LO2 signal to produce an IL2 signal;

a fourth MULTIPLIER MEANS for multiplying said L2 signal with a quadrature (Q) version of said 2-nd LO2 signal to produce a QL2 signal;

a first AMPLIFIER MEANS connected to said first MULTIPLIER MEANS for amplifying said IL1 signal;

a second AMPLIFIER MEANS connected to said second MULTIPLIER MEANS for amplifying said QL1 signal;

a third AMPLIFIER MEANS connected to said third MULTIPLIER MEANS for amplifying said IL2 signal;

a fourth AMPLIFIER MEANS connected to said fourth MULTIPLIER MEANS for amplifying said QL2 signal;

a first one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said first AMPLIFIER MEANS for performing 1-bit quantization operation on said IL1 signal;

a second one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said second AMPLIFIER MEANS for performing 1-bit quantization operation on said QL1 signal;

a third one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said third AMPLIFIER MEANS for performing 1-bit quantization operation on said IL2 signal;

a fourth one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said fourth AMPLIFIER MEANS for performing 1-bit quantization operation on said QL2 signal;

a FLIP-FLOP MEANS (FF1) connected to said first one-bit A/D CONVERTER for sampling said IL1 signal, wherein said sampling operation is performed by clocking said IL1 signal through said FF1 at sampling clock (SCLK) rate;

a second FLIP-FLOP MEANS (FF2) connected to said second one-bit A/D CONVERTER for sampling said QL1 signal, wherein said sampling operation is performed by clocking said QL1 signal through said FF2 at sampling clock (SCLK) rate;

a third FLIP-FLOP MEANS (FF3) connected to said third one-bit A/D CONVERTER for sampling said IL2 signal, wherein said sampling operation is performed by clocking said IL2 signal through said FF3 at sampling clock (SCLK) rate; and

a fourth FLIP-FLOP MEANS (FF4) connected to said fourth one-bit A/D CONVERTER for sampling said QL2 signal, wherein said sampling operation is performed by clocking said QL2 signal through said FF4 at sampling clock (SCLK) rate; and

wherein each said DIGITAL CHANNEL PROCESSING MEANS further comprises;

a L1 TRACKER MEANS for tracking L1 C/A code when Y code is ON and for tracking L1 P code when Y code is OFF;

an L2 TRACKER MEANS connected to said L1 TRACKER MEANS for tracking an enhanced cross correlated W code when Y code is ON and for tracking L2 P code when Y code is OFF; and

a MICROPROCESSOR MEANS system connected to said L1 TRACKER MEANS and to said L2 TRACKER MEANS;

wherein said L1 TRACKER MEANS is fed by digitized inphase IL1 and quadrature QL1 of L1 signal outputted by said IF PROCESSOR MEANS; and

wherein said L2 TRACKER MEANS is fed by digitized inphase I L2 and quadrature QL2 of L2 signal outputted by said IF PROCESSOR MEANS; and

wherein each said L1 and L2 TRACKER MEANS are synchronously clocked said SCLK signal and synchronously referenced by said MSEC signal to local reference time;

said SCLK and MSEC signals being outputted by said FREQUENCY SYNTHESIZER MEANS; and

wherein said L2 TRACKER MEANS when Y code is ON is fed from said L1 TRACKER MEANS by generated by said L1 TRACKER MEANS three signals;

L1 P code, filtered estimate of L1 W code, and C/A code epoch (EP code); and

wherein said MICROPROCESSOR MEANS system is fed by output signals from said L1 TRACKER MEANS and said L2 TRACKER MEANS; and

wherein said L1 TRACKER MEANS and said L2 TRACKER MEANS are fed by control signal from said MICROPROCESSOR MEANS; and

wherein said L1 TRACKER MEANS further comprises;

a CODE GENERATOR MEANS for providing a locally generated replica of C/A code and P code;

a MULTIPLEXER MEANS 1 connected to said CODE GENERATOR MEANS for selecting a locally generated code C/A when Y code is ON and for selecting a locally generated P code when Y code is OFF, said MULTIPLEXER MEANS 1 being controlled by said MICROPROCESSOR MEANS system;

a carrier numerically controlled oscillator (CARRIER NCO MEANS

     1) connected to said MULTIPLEXER MEANS 1;

a CARRIER MIXER MEANS 1 connected to said CARRIER NCO MEANS 1 for multiplying outputted by said IF PROCESSOR MEANS digitized inphase IL1 and Q L1 signals having carrier frequency with outputted by said CARRIER NCO MEANS 1 inphase and quadrature components of digital carrier;

wherein said CARRIER MIXER MEANS 1 outputs inphase IL1 and quadrature Q L1 signals having zero carrier frequency;

a CODE MIXER MEANS 1 connected to said CARRIER MIXER MEANS 1, connected to said CODE GENERATOR MEANS and connected to said CARRIER NCO MEANS 1 for code correlating said CARRIER MIXER MEANS 1 output signals with said locally generated replica of C/A code;

wherein when said L1 TRACKER MEANS '"'"'s carrier tracking loop is closed via said CARRIER NCO MEANS 1 the input to said CODE MIXER MEANS 1 represents the satellite signal L1 C/A code; and

wherein said CODE MIXER MEANS 1 performs said code correlation at 3 time points (early, punctual and late) on the autocorrelation function graph creating an early, a punctual and a late sample of the autocorrelation function;

a block CORRELATORS MEANS 1 connected to said CODE MIXER MEANS 1 for integrating said early, punctual and late samples of said autocorrelation function;

wherein said CORRELATORS MEANS 1 output signal is fed to said MICROPROCESSOR MEANS system at a rate of L1 C/A code epoch, and wherein said MICROPROCESSOR MEANS uses said CORRELATORS MEANS 1 output signal to develop feedback signals for the carrier tracking loop and for the code tracking loop;

a code numerically controlled oscillator (CODE NCO MEANS) connected to said block CORRELATORS MEANS 1 and connected to said CODE GENERATOR MEANS for providing a clocking signal at C/A code rate and for providing a clocking signal at P code rate, said C/A code clocking rate and said P code clocking rate driving said CODE GENERATOR MEANS;

said CODE NCO MEANS also providing a mechanism for aligning said locally generated replica of C/A code with said incoming satellite C/A code;

a CODE MIXER MEANS 2 connected to said CARRIER MIXER MEANS 1 and connected to said CODE GENERATOR MEANS said CARRIER MIXER MEANS 1 outputting an estimate of L1 Y code as an input to said CODE MIXER MEANS 2, said CODE GENERATOR MEANS outputting said local replica of known L1 P code as input to said CODE MIXER MEANS 2, wherein said CODE MIXER MEANS 2 removes known L1 P code from said estimate of L1 Y code and outputs an estimate of L1 W code;

a DIGITAL DELAY MEANS 1 connected to said CODE MIXER MEANS 2 for delaying under said MICROPROCESSOR MEANS system control said L1 W code estimate;

a DIGITAL FILTER MEANS 1 connected to said DIGITAL DELAY MEANS 1 for reducing the bandwidth of said L1 W code estimate;

wherein said delayed and filtered L1 W code estimate is sent for processing to said L2 TRACKER MEANS;

a DIGITAL DELAY MEANS 2 connected to said CODE GENERATOR MEANS for delaying said P code output from said CODE GENERATOR MEANS, wherein said delayed P code is sent to said L2 TRACKER MEANS; and

a RESOLVER MEANS connected to said CARRIER NCO MEANS 1 for toggling the digital delay between the two delays in the DIGITAL DELAY 1 and in the DIGITAL DELAY 2, wherein the resulting delay is the average of the relative time spent on each said delay;

and wherein said L1 C/A code epoch (EP) is sent to said L2 TRACKER MEANS; and

wherein said L2 TRACKER MEANS further comprises;

a carrier numerically controlled oscillator (CARRIER NCO MEANS

     2);

a CARRIER MIXER MEANS 2 connected to said CARRIER NCO MEANS 2 for mixing outputted by said IF PROCESSOR MEANS digitized inphase I L2 and Q L2 signals having carrier frequency with outputted by said CARRIER NCO MEANS 2 inphase and quadrature components of digital carrier;

wherein said CARRIER MIXER MEANS 2 outputs inphase I L2 and quadrature Q L2 signals having zero carrier frequency; and

wherein when L2 carrier tracking loop is locked via said CARRIER NCO MEANS 2 said I L2 output contains an estimate of L2 Y code and said Q L2 output contains no signal power;

a CODE MIXER MEANS 3 connected to said CARRIER MIXER MEANS 2 for code correlating said CARRIER MIXER MEANS 2 output I and Q signals with outputted by said L1 TRACKER MEANS P1 code, wherein said P1 code represents a locally generated replica of L2 P code, and wherein said CODE MIXER MEANS 3 outputs an I estimate of L2 W code and a Q estimate of L2 W code;

a DIGITAL FILTER MEANS 2 connected to said CODE MIXER MEANS 3 for reducing the bandwidth of said I estimate of L2 W code;

a DIGITAL FILTER MEANS 3 connected to said CODE MIXER MEANS 3 for reducing the bandwidth of said Q estimate of L2 W code;

a CODE MIXER MEANS 4 connected to said DIGITAL FILTER MEANS 2 and connected to said DIGITAL FILTER MEANS 3 for correlating said estimate of L2 W code and said Q estimate of L2 W code with a signal W1, wherein said signal W1 is said estimate of L1 W code sent by said L1 TRACKER MEANS; and

wherein said CODE MIXER MEANS 4 performs said code correlation at 3 time points (early, punctual and late) on the autocorrelation function graph creating an early, a punctual and a late sample of the autocorrelation function;

a CODE MIXER MEANS 5 connected to said CARRIER MIXER MEANS 2 for code correlating said CARRIER MIXER MEANS 2 output I and Q signals with outputted by said L1 TRACKER MEANS P1 code, wherein said P1 code represents a locally generated replica of L2 P code, and wherein said CODE MIXER MEANS 5 performs said code correlation at 3 time points (early, punctual and late) on the autocorrelation function graph creating an early, a punctual and a late sample of the autocorrelation function;

a MULTIPLEXER MEANS 2 connected to said CODE MIXER MEANS 5 and connected to said CODE MIXER MEANS 4 for selecting under the control of MICROPROCESSOR MEANS the mode of operation when Y code is ON and OFF; and

wherein when Y code is OFF and satellite transmits the P code on L2 said MICROPROCESSOR MEANS selects the output of CODE MIXER MEANS 5; and

wherein when Y code is ON said MICROPROCESSOR MEANS selects the output of CODE MIXER MEANS 4; and

a block CORRELATORS MEANS 2 connected to said MULTIPLEXER MEANS 2 for integrating said early, punctual and late samples of said autocorrelation function;

wherein said CORRELATORS MEANS 2 output signal is fed to said MICROPROCESSOR MEANS system at a rate of sent by said L1 TRACKER MEANS said L1 C/A code epoch (EP), and wherein said MICROPROCESSOR MEANS uses said CORRELATORS MEANS 2 output signal to develop feedback signals for the carrier tracking loop and for the code tracking loop; and

wherein said DIGITAL FILTER MEANS 2 further comprises a finite impulse response (FIR) DIGITAL FILTER 2; and

wherein said FIR DIGITAL FILTER 2 performs the enhanced cross correlation operation by matching the observed W-code spectrum and by optimizing the signal-to-noise (STN) ratio of the cross-correlation process.

12. The system of claim 11, wherein said FIR DIGITAL FILTER 2 is implemented using a direct form transfer function.

13. The system of claim 11, wherein said FIR DIGITAL FILTER 2 is implemented using a cascade form transfer function.

19. The system of claim 11, wherein said FIR DIGITAL FILTER 2 further comprises

a first L-bit SHIFT REGISTER MEANS (X1 ,X2, . . . Xm), m being an integer, for making an m- number of delayed copies of an input signal X, wherein a first copy of said input signal X1 is delayed by one sample clock SCLK, a second copy of said input signal X2 is delayed by two sample clocks, an (i) copy of said input signal Xi is delayed by (i) sample clocks, i being an integer, and an m-copy of said input signal Xm is delayed by (m) sample clocks;

an m-number of MULTIPLIER MEANS (C1, . . . Cm), wherein a first MULTIPLIER MEANS C1 transforms said X1 signal into a C1X1 signal; and

wherein a second MULTIPLIER MEANS C2transforms said X2 signal into a C2X2 signal, and wherein an (i) MULTIPLIER MEANS Ci transform said Xi signal into a CiXi signal, and wherein an (m) MULTIPLIER MEANS transforms said Xm signal into a CmXm signal;

and an ADDER MEANS connected to each of said Ci MULTIPLIER MEANS for adding each said CiXi signals into an output function Yout, wherein said output function Yout is equal to;

space="preserve" listing-type="equation">Yout=C1X1+C2X2+ . . . CmXm;

wherein said FIR DIGITAL FILTER MEANS 2 optimizes the signal-to-noise ratio by adapting to changes in the input signal X frequency spectrum.

15. A system for optimum correlation processing of L1 and L2 signals received from a SPS satellite by a SPS RECEIVER, said system comprising:

a RECEIVING MEANS for receiving a known C/A code modulated on L1 carrier frequency, for receiving an unknown Y code modulated on L1 carrier frequency signal, and for receiving an unknown Y code modulated on L2 carrier frequency signal from at least one satellite;

wherein said received L1 , and L2 signals contain propagation noise; and

wherein said Y code comprises a known P code and an unknown W code; and

at least one DIGITAL CHANNEL PROCESSING MEANS for;

(1) locally generating replica of said C/A code modulated on L1 carrier frequency signal;

(2) locally generating replica of said P code modulated on L1 carrier frequency signal, wherein said locally generated replica of L1 signal do not contain propagation noise;

(3) extracting of an estimate of said Y code from said L1 signal, and from said L2 signal, wherein said estimate signals contain propagation noise;

(4) correlating a locally generated replica of C/A code with the received L1 code for obtaining an estimate of L1 group delay (L1 pseudo-range) and L1 carrier phase;

(5) removing said P code from said locally extracted estimate of said L1 Y code to obtain a locally extracted estimate of said L1 W code;

(6) removing said P code from said locally extracted estimate of said L2 Y code to obtain a locally extracted estimate of said L2 W code; and

(7) correlating said locally extracted estimate of said L1 W code with said locally extracted estimate of said L2 W code to obtain relative offset in group delay between L1 and L2 signals and for obtaining an independent estimate of L2 carrier phase; and

where in said RECEIVING MEANS further comprises;

a dual frequency patch ANTENNA MEANS for receiving said L1 and L2 satellite signals;

a FILTER/LNA MEANS conductively connected to said ANTENNA MEANS for performing filtering and low noise amplification of said L1 and L2 signals, wherein said FILTER/LNA determines the noise/signal ratio of the received signals L1 and L2;

a DOWNCONVERTER MEANS conductively connected to said FILTER/LNA MEANS for mixing and converting said L1 and L2 signals; and

an IF PROCESSOR MEANS conductively connected to said DOWNCONVERTER MEANS for transforming said converted L1 and L2 signals into digitally sampled quadrature versions of L1 and L2 signals (IL1 , QL1 , IL2 , QL2 );

a MASTER OSCILLATOR MEANS; and

a FREQUENCY SYNTHESIZER MEANS conductively connected to said MASTER OSCILLATOR MEANS, to said IF PROCESSOR MEANS, to said DOWNCONVERTER MEANS, and to at least one said DIGITAL, CHANNEL, PROCESSING MEANS, wherein said FREQUENCY SYNTHESIZER MEANS generates several timing signals; and

wherein said IF PROCESSOR MEANS further comprises;

a first POWER SPLITTER MEANS connected to said DOWNCONVERTER MEANS and to said FREQUENCY SYNTHESIZER MEANS for power splitting said L1 signal into two signals;

a second POWER SPLITTER MEANS connected to said DOWNCONVERTER MEANS and to said FREQUENCY SYNTHESIZER MEANS for power splitting said L2 signal into two signals;

a first MULTIPLIER MEANS for multiplying said L1 signal with an inphase (I) version of said 2-nd LO2 signal to produce an IL1 signal;

a second MULTIPLIER MEANS for multiplying said L1 signal with a quadrature (Q) version of said 2-nd LO2 signal to produce a QL1 signal;

a third MULTIPLIER MEANS for multiplying said L2 signal with an inphase (I) version of said 2-nd LO2 signal to produce an IL2 signal;

a fourth MULTIPLIER MEANS for multiplying said L2 signal with a quadrature (Q) version of said 2-nd LO2 signal to produce a QL2 signal;

a first AMPLIFIER MEANS connected to said first MULTIPLIER MEANS for amplifying said IL1 signal;

a second AMPLIFIER MEANS connected to said second MULTIPLIER MEANS for amplifying said QL1 signal;

a third AMPLIFIER MEANS connected to said third MULTIPLIER MEANS for amplifying said IL2 signal;

a fourth AMPLIFIER MEANS connected to said fourth MULTIPLIER MEANS for amplifying said QL2 signal;

a first one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said first AMPLIFIER MEANS for performing 1-bit quantization operation on said IL1 signal;

a second one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said second AMPLIFIER MEANS for performing 1-bit quantization operation on said QL1 signal;

a third one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said third AMPLIFIER MEANS for performing 1-bit quantization operation on said IL2 signal;

a fourth one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said fourth AMPLIFIER MEANS for performing 1-bit quantization operation on said QL2 signal;

a first FLIP-FLOP MEANS (FF1) connected to said first one-bit A/D CONVERTER for sampling said IL1 signal, wherein said sampling operation is performed by clocking said IL1 signal through said FF1 at sampling clock (SCLK) rate;

a second FLIP-FLOP MEANS (FF2) connected to said second one-bit A/D CONVERTER for sampling said QL1 signal, wherein said sampling operation is performed by clocking said QL1 signal through said FF2 at sampling clock (SCLK) rate;

a third FLIP-FLOP MEANS (FF3) connected to said third one-bit A/D CONVERTER for sampling said IL2 signal, wherein said sampling operation is performed by clocking said IL2 signal through said FF3 at sampling clock (SCLK) rate; and

a fourth FLIP-FLOP MEANS (FF4) connected to said fourth one-bit A/D CONVERTER for sampling said QL2 signal, wherein said sampling operation is performed by clocking said QL2 signal through said FF4 at sampling clock (SCLK) rate; and

wherein each said DIGITAL CHANNEL PROCESSING MEANS further comprises;

an L1 TRACKER MEANS for tracking L1 C/A code when Y code is ON and for tracking L1 P code when Y code is OFF;

an L2 TRACKER MEANS connected to said L1 TRACKER MEANS for tracking an enhanced cross correlated W code when Y code is ON and for tracking L2 P code when Y code is OFF; and

a MICROPROCESSOR MEANS system connected to said L1 TRACKER MEANS and to said L2 TRACKER MEANS;

wherein said L1 TRACKER MEANS is fed by digitized inphase IL1 and quadrature QL1 of L1 signal outputted by said IF PROCESSOR MEANS; and

wherein said L2 TRACKER MEANS is fed by digitized inphase I L2 and quadrature QL2 of L2 signal outputted by said IF PROCESSOR MEANS; and

wherein each said L1 and L2 TRACKER MEANS are synchronously clocked by said SCLK signal and synchronously referenced by said MSEC signal to local reference time;

said SCLK and MSEC signals being outputted by said FREQUENCY SYNTHESIZER MEANS; and

wherein said L2 TRACKER MEANS when Y code is ON is fed from said L1 TRACKER MEANS by generated by said L1 TRACKER MEANS three signals;

L1 P code, filtered estimate of L1 W code, and C/A code epoch (EP code); and

wherein said MICROPROCESSOR MEANS system is fed by output signals from said L1 TRACKER MEANS and said L2 TRACKER MEANS; and

wherein said L1 TRACKER MEANS and said L2 TRACKER MEANS are by control signal from said MICROPROCESSOR MEANS; and

wherein said L1 TRACKER MEANS further comprises;

a CODE GENERATOR MEANS for providing a locally generated replica of C/A code and P code;

a MULTIPLEXER MEANS 1 connected to said CODE GENERATOR MEANS for selecting a locally generated code C/A when Y code is ON and for selecting a locally generated P code when Y code is OFF, said MULTIPLEXER MEANS 1 being controlled by said MICROPROCESSOR MEANS system;

a carrier numerically controlled oscillator (CARRIER NCO MEANS

     1) connected to said MULTIPLEXER MEANS 1;

a CARRIER MIXER MEANS 1 connected to said CARRIER NCO MEANS 1 for multiplying outputted by said IF PROCESSOR MEANS digitized inphase IL1 and Q L1 signals having carrier frequency with outputted by said CARRIER NCO MEANS 1 inpha quadrature components of digital carrier;

wherein said CARRIER MIXER MEANS 1 outpub inphase IL1 and quadrature Q L1 signals having zero carrier frequency;

a CODE MIXER MEANS 1 connected to said CARRIER MIXER MEANS 1, connected to said CODE GENERATOR MEANS and connected to said CARRIER NCO MEANS 1 for code correlating said CARRIER MIXER MEANS 1 output signals with said locally generated replica of C/A code wherein when said L1 TRACKER MEANS '"'"'s carrier tracking loop is closed via said CARRIER NCO MEANS 1 the input to said CODE MIXER MEANS 1 represents the satellite signal L1 C/A code; and

wherein said CODE MIXER MEANS 1 performs said code correlation at 3 time points (early, punctual and late) on the autocorrelation function graph creating an early, a punctual and a late sample of the autocorrelation function;

a block CORRELATORS MEANS 1 connected to said CODE MIXER MEANS 1 for integrating said early, punctual and late samples of said autocorrelation function;

wherein said CORRELATORS MEANS 1 output signal is fed to said MICROPROCESSOR MEANS system at a rate of L1 C/A code epoch, and wherein said MICROPROCESSOR MEANS uses said CORRELATORS MEANS 1 output signal to develop feedback signals for the carrier tracking loop and for the code tracking loop;

a code numerically controlled oscillator (CODE NCO MEANS) connected to said block CORRELATORS MEANS 1 and connected to said CODE GENERATOR MEANS for providing a clocking signal at C/A code rate and for providing a clocking signal at P code rate, said C/A code clocking rate and said P code clocking rate driving said CODE GENERATOR MEANS;

said CODE NCO MEANS also providing a mechanism for aligning said locally generated replica of C/A code with said incoming satellite C/A code;

a CODE MIXER MEANS 2 connected to said CARRIER MIXER MEANS 1 and connected to said CODE GENERATOR MEANS, said CARRIER MIXER MEANS 1 outputting an estimate of L1 Y code as an input to said CODE MIXER MEANS 2, said CODE GENERATOR MEANS outputting said local replica of known L1 P code as input to said CODE MIXER MEANS 2, wherein said CODE MIXER MEANS 2 removes known L1 P code from said estimate of L1 Y code and outputs an estimate of L1 W code;

a DIGITAL DELAY MEANS 1 connected to said CODE MIXER MEANS 2 for delaying under said MICROPROCESSOR MEANS system control said L1 W code estimate;

a DIGITAL FILTER MEANS 1 connected to said DIGITAL DELAY MEANS 1 for reducing the bandwidth of said L1 W code estimate;

wherein said delayed and filtered L1 W code estimate is sent for processing to said L2 TRACKER MEANS;

a DIGITAL DELAY MEANS 2 connected to said CODE GENERATOR MEANS for delaying said P code output from said CODE GENERATOR MEANS, wherein said delayed P code is sent to said L2 TRACKER MEANS; and

a RESOLVER MEANS connected to said CARRIER NCO MEANS 1 for toggling the digital delay between the two delays in the DIGITAL DELAY 1 and in the DIGITAL DELAY 2, wherein the resulting delay is the average of the relative time spent on each said delay;

and wherein said L1 C/A code epoch (EP) is sent to said L2 TRACKER MEANS; and

wherein said L2 TRACKER MEANS further comprises;

a carrier numerically controlled oscillator (CARRIER NCO MEANS

     2);

a CARRIER MIXER MEANS 2 connected to said CARRIER NCO MEANS 2 for mixing outputted by said IF PROCESSOR MEANS digitized inphase I L2 and Q L2 signals having carrier frequency with outputted by said CARRIER NCO MEANS 2 inphase and quadrature components of digital carrier;

wherein said CARRIER MIXER MEANS 2 outputs inphase I L2 and quadrature Q L2 signals having zero carrier frequency; and

wherein when L2 carrier tracking loop is locked via said CARRIER NCO MEANS 2 said I L2 output contains an estimate of L2 Y code and said Q L2 output contains no signal power;

a CODE MIXER MEANS 3 connected to said CARRIER MIXER MEANS 2 for code correlating said CARRIER MIXER MEANS 2 output I and Q signals with outputted by said L1 TRACKER MEANS P1 code, wherein said P1 code represents a locally generated replica of L2 P code, and wherein said CODE MIXER MEANS 3 outputs an I estimate of L2 W code and a Q estimate of L2 W code;

a DIGITAL FILTER MEANS 2 connected to said CODE MIXER MEANS 3 for reducing the bandwidth of said I estimate of L2 W code;

a DIGITAL FILTER MEANS 3 connected to said CODE MIXER MEANS 3 for reducing the bandwidth of said Q estimate of L2 W code;

a CODE MIXER MEANS 4 connected to said DIGITAL FILTER MEANS 2 and connected to said DIGITAL FILTER MEANS 3 for correlating said I estimate of L2 W code and said Q estimate of L2 W code with a signal W1, wherein said signal W1 is said estimate of L1 W code sent by said L1 TRACKER MEANS; and

wherein said CODE MIXER MEANS 4 performs said code correlation at 3 time points (early, punctual and late) on the autocorrelation function graph creating an early, a punctual and a late sample of the autocorrelation function;

a CODE MIXER MEANS 5 connected to said CARRIER MIXER MEANS 2 for code correlating said CARRIER MIXER MEANS 2 output I and Q signals with outputted by said L1 TRACKER MEANS P1 code, wherein said P1 code represents a locally generated replica of L2 P code; and

wherein said CODE MIXER MEANS 5 performs said code correlation at 3 time points (early, punctual and late) on the autocorrelation function graph creating an early;

a punctual and a late sample of the autocorrelation function;

a MULTIPLEXER MEANS 2 connected to said CODE MIXER MEANS 5 and connected to said CODE MIXER MEANS 4 for selecting, under the control of MICROPROCESSOR MEANS the mode of operation when Y code is ON and OFF; and

wherein when Y code is OFF and satellite transmits the P code on L2 said MICROPROCESSOR MEANS selects the output of CODE MIXER MEANS 5; and

wherein when Y code is ON said MICROPROCESSOR MEANS selects the output of CODE MIXER MEANS 4; and

a block CORRELATORS MEANS 2 connected to said MULTIPLEXER MEANS 2 for integrating said early, punctual and late samples of said autocorrelation function;

wherein said CORRELATORS MEANS 2 output signal is fed to said MICROPROCESSOR MEANS system at a rate of sent by said L1 TRACKER MEANS said L1 C/A code epoch (EP), and wherein said MICROPROCESSOR MEANS uses said CORRELATORS MEANS 2 output signal to develop feedback signals for the carrier tracking loop and for the code tracking loop; and

wherein said DIGITAL FILTER MEANS 2 further comprises an infinite impulse response (IIR) DIGITAL FILTER 2; and

wherein said IIR DIGITAL FILTER 2 performs the enhanced cross correlation operation by matching the observed W-code spectrum and by optimizing the signal-to-noise (STN) ratio of the cross-correlation process.

16. The system of claim 15, wherein said IIR DIGITAL FILTER 2 is implemented using a direct form transfer function.

17. The system of claim 15, wherein said IIR DIGITAL FILTER 2 is implemented using a cascade form transfer function.

18. The system of claim 15, wherein said IIR DIGITAL FILTER 2 is implemented using a parallel form transfer function.

20. The system of claim 15, wherein said IIR DIGITAL FILTER 2 further comprises

a first L-bit SHIFT REGISTER MEANS (X1 ,X2, . . . Xm), m being an integer, for making an m- number of delayed copies of an input signal X, wherein said input signal X comprises said I estimate of L2 W code, and wherein a first copy of said input signal X1 is delayed by one sample clock SCLK, a second copy of said input signal X2 is delayed by two sample clocks, an (i) copy of said input signal Xi is delayed by (i) sample clocks, i being an integer, and an m-copy of said input signal Xm is delayed by (m) sample clocks;

an m-number of MULTIPLIER MEANS (C1, . . . Cm), wherein a first MULTIPLIER MEANS C1 transforms said X1 signal into a C1X1 signal; and

wherein a second MULTIPLIER MEANS C2transforms said X2 signal into a C2X2 signal, and wherein an (i) MULTIPLIER MEANS Ci transform said Xi signal into a CiXi signal, and wherein an (M) MULTIPLIER MEANS transforms said Xm signal into a CmXm signal;

a second L-bit SHIFT REGISTER MEANS (Y1,Y2 , . . . Yn), n being an integer, for making an n- number of delayed copies of an output signal Y, and wherein a first copy of said output signal Y1 is delayed by one sample clock SCLK, a second copy of said output signal Y2 is delayed by two sample clocks, an (i) copy of said output signal Yi is delayed by (i) sample clocks, i being an integer, and an n-copy of said output signal Yn is delayed by (n) sample clocks;

an n-number of MULTIPLIER MEANS (B1, . . . Bn), wherein a first MULTIPLIER MEANS B1 transforms said Y1 signal into a B1Y1 signal; and

wherein a second MULTIPLIER MEANS B2 transforms said Y2 signal into a B2Y2 signal, and wherein an (i) MULTIPLIER MEANS Bi transform said Yi signal into a BiYi signal, and wherein an (n) MULTIPLIER MEANS Bn transforms said Yn signal into a BnYn signal;

and an ADDER MEANS connected to each of said Ci and Bi MULTIPLIER MEANS for adding each said CiXi and BiYi signals into an output function Yout, wherein said output function Yout is equal to;

space="preserve" listing-type="equation">Yout=C1X1+C2X2+ . . . +CmXm+B1Y1+B2Y2+ . . . +BnYn;

and wherein said FIR DIGITAL FILTER MEANS 2 optimizes the signal-to-noise ratio by adapting to changes in the input signal X frequency spectrum.