SRAM with simplified architecture for use with pipelined data

• US 5,621,695 A
• Filed: 07/17/1995
• Issued: 04/15/1997
• Est. Priority Date: 07/17/1995
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Galvantech Inc (Infineon Technologies AG)
• Inventors: Tran, Thinh D.
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): NIRANJAN, FRANK
• Application Number:
  US08/502,974
• Time in Patent Office: 638 Days
• Field of Search: 365/189.05, 365/221, 365/230.09, 365/230.03, 365/233
• US Class Current: 365/189.02
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers

Abstract

A high speed high capacity SRAM having a density of 256K bits or larger. Individual complementary memory cell pairs are arranged in memory blocks and are directly accessed during write and read operations by input/output circuitry having an input buffer, write driver circuits, sense amplifiers, an output buffer and an output register. Data is read from individual memory blocks using a pipelined read data mode in which data accessed by a row, column and block address during a first cycle is stored in an output (pipeline) register at the beginning of the next cycle. In one embodiment all components of the data input/output circuits are located remotely from the memory blocks and paired data lines are used. In an alternate embodiment, the input buffer, a pipeline register and output buffer components of the data input/output circuits are remotely located, and these components are coupled via single data lines and multiplexers to local write drive and sense amplifier circuits located closely adjacent the individual memory blocks. The SRAM is capable of comparable performance to a divided word line SRAM using modular architecture, but has a much simpler design requiring less area.

Claims

1. A high speed high density SRAM for providing random access to stored data in a pipelined read data mode of operation, said SRAM comprising:

row, column and block address circuitry for receiving pipelined row, column and block address information during a pipelined read operation;

a plurality of memory arrays each having a plurality of memory cells and a plurality of word lines and bit lines coupled to individual ones of said memory cells, the total capacity of said plurality of memory arrays being at least 256K bits;

a plurality of block word line select logic circuits each associated to a different one of said plurality of arrays of memory cells and coupled to said row and block address circuitry for selecting individual ones of said word lines in response to receipt of row and block address information;

a plurality of column select logic circuits each associated to a different one of said plurality of arrays of memory cells and coupled to said column and block address circuitry for selecting individual ones of said bit lines in response to receipt of column and block address information;

data input/output circuitry for manifesting in pipelined form data read from individual memory cells specified by said row, column and block address information; and

a plurality of data lines coupled between said input/output circuitry and said plurality of memory arrays, said SRAM being devoid of secondary sense amplifiers and secondary write drivers whereby data is read directly from said plurality of memory arrays in pipelined mode, said data input/output circuitry including a plurality of read/write interface circuits, each interface circuit including a data input buffer, a data output buffer, a data input write driver coupled to said data input buffer and coupled directly to selected ones of the memory cells in a memory array selected during a write operation, a sense amplifier coupled directly to selected ones of the memory cells during a read operation, and an output register coupled between said sense amplifier and said data output buffer.

2. A high speed high density SRAM for providing random access to stored data in a pipelined read data mode of operation, said SRAM comprising:

row, column and block address circuitry for receiving pipelined row, column and block address information during a pipelined read operation;

a plurality of memory arrays each having a plurality of memory cells and a plurality of word lines and bit lines coupled to individual ones of said memory cells, the total capacity of said plurality of memory arrays being at least 256K bits;

a plurality of block word line select logic circuits each associated to a different one of said plurality of arrays of memory cells and coupled to said row and block address circuitry for selecting individual ones of said word lines in response to receipt of row and block address information;

a plurality of column select logic circuits each associated to a different one of said plurality of arrays of memory cells and coupled to said column and block address circuitry for selecting individual ones of said bit lines in response to receipt of column and block address information;

data input/output circuitry for manifesting in pipelined form data read from individual memory cells specified by said row, column and block address information; and

a plurality of data lines coupled between said input/output circuitry and said plurality of memory arrays, said SRAM being devoid of secondary sense amplifiers and secondary write drivers whereby data is read directly from said plurality of memory arrays in pipelined mode, said data input/output circuitry including a plurality of read/write buffering circuits, each buffering circuit including an input data buffer, an output data buffer and an output register;

said SRAM further including a plurality of read/write circuits each associated to a different one of said memory arrays and each coupled to said data input/output circuitry via said plurality of data lines, each said read/write circuit including a multiplexer coupled to said data lines, a plurality of data input write drivers coupled to said data input buffers via said multiplexer and said data lines and coupled directly to selected ones of the memory cells in the associated memory array during a write operation, and a plurality of sense amplifiers coupled to said data output buffers via said multiplexer and said data lines and coupled directly to selected ones of the memory cells in the associated memory array during a read operation.