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Method and apparatus for testing semiconductor integrated circuit devices

  • US 5,621,742 A
  • Filed: 06/07/1995
  • Issued: 04/15/1997
  • Est. Priority Date: 12/22/1992
  • Status: Expired due to Fees
First Claim
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1. A method for testing a semiconductor integrated circuit device, comprising the steps of:

  • (a) supplying a power supply voltage to the semiconductor integrated circuit device;

    (b) intermittently generating a latch up pulse in the power supply voltage to the semiconductor integrated circuit device;

    (c) determining whether a latch up condition is present in the semiconductor integrated circuit device;

    (d) temporarily cutting off the power supply voltage to the semiconductor integrated circuit device when the latch up condition is present;

    (e) resupplying the power supply voltage to the semiconductor integrated circuit device;

    (f) generating additional latch up pulses in the power supply voltage;

    (g) determining whether additional latch up conditions are present in the semiconductor integrated circuit device within a predetermined number of the additional latch up pulses;

    (h) cutting off the power supply to the semiconductor integrated circuit device when a predetermined number of additional latch up conditions are present in the predetermined number of additional latch up pulses; and

    (i) repeating steps (b-h) when the additional latch up conditions do not occur in the predetermined number of latch up pulses.

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