Method and apparatus for testing semiconductor integrated circuit devices
First Claim
1. A method for testing a semiconductor integrated circuit device, comprising the steps of:
- (a) supplying a power supply voltage to the semiconductor integrated circuit device;
(b) intermittently generating a latch up pulse in the power supply voltage to the semiconductor integrated circuit device;
(c) determining whether a latch up condition is present in the semiconductor integrated circuit device;
(d) temporarily cutting off the power supply voltage to the semiconductor integrated circuit device when the latch up condition is present;
(e) resupplying the power supply voltage to the semiconductor integrated circuit device;
(f) generating additional latch up pulses in the power supply voltage;
(g) determining whether additional latch up conditions are present in the semiconductor integrated circuit device within a predetermined number of the additional latch up pulses;
(h) cutting off the power supply to the semiconductor integrated circuit device when a predetermined number of additional latch up conditions are present in the predetermined number of additional latch up pulses; and
(i) repeating steps (b-h) when the additional latch up conditions do not occur in the predetermined number of latch up pulses.
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Accused Products
Abstract
A method and apparatus for testing a semiconductor integrated circuit device is described. During an aging test of the integrated circuit device, a situation, in which latch up of the semiconductor integrated circuit device can occur, is intermittently created by intermittently supplying a pulse of a power supply voltage Vb, which is higher than a normal voltage Va in accordance with a rated power supply voltage of the tested integrated circuit device. The power supply to the tested semiconductor integrated circuit device is temporarily cut off when latch up occurs. If a second latch up occurs after a restart of the aging test, it is determined that there is an abnormality in the tested semiconductor integrated circuit device. The power supply to the tested semiconductor integrated circuit device is permanently cut off in response to this determination. This prevents damage to the test-object integrated semiconductor device and permits later determination of the degree to which the device is latch up immune.
18 Citations
17 Claims
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1. A method for testing a semiconductor integrated circuit device, comprising the steps of:
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(a) supplying a power supply voltage to the semiconductor integrated circuit device; (b) intermittently generating a latch up pulse in the power supply voltage to the semiconductor integrated circuit device; (c) determining whether a latch up condition is present in the semiconductor integrated circuit device; (d) temporarily cutting off the power supply voltage to the semiconductor integrated circuit device when the latch up condition is present; (e) resupplying the power supply voltage to the semiconductor integrated circuit device; (f) generating additional latch up pulses in the power supply voltage; (g) determining whether additional latch up conditions are present in the semiconductor integrated circuit device within a predetermined number of the additional latch up pulses; (h) cutting off the power supply to the semiconductor integrated circuit device when a predetermined number of additional latch up conditions are present in the predetermined number of additional latch up pulses; and (i) repeating steps (b-h) when the additional latch up conditions do not occur in the predetermined number of latch up pulses. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A non-destructive testing apparatus for a semiconductor integrated circuit device, comprising:
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a pulse power supply for supplying voltage to the semiconductor integrated circuit device; a current measuring circuit for measuring a current flowing in the semiconductor integrated circuit device; an abnormal condition determining circuit for determining an abnormal current condition in the semiconductor integrated circuit device based on the measured current, and for outputting a power supply cut off signal upon determining an abnormal current condition exists; and a current limiting circuit for receiving the power supply cut off signal and for turning off the pulse power supply in response to the power supply cut off signal; wherein the abnormal condition circuit temporarily outputs the power supply cut off signal after each of a first predetermined number of abnormal current conditions are determined and permanently outputs the power supply cut off signal after a second predetermined number of abnormal current conditions are determined, wherein the second predetermine number is greater than the first predetermined number. - View Dependent Claims (13, 14, 15, 16, 17)
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Specification