Device for justifying a digital bit stream at regular intervals

• US 5,621,775 A
• Filed: 10/18/1994
• Issued: 04/15/1997
• Est. Priority Date: 10/20/1993
• Status: Expired due to Term

• Current Assignee: Alcatel-Lucent France, SA (Nokia Corporation)
• Original Assignee: Alcatel-Lucent France, SA (Nokia Corporation)
• Inventors: Etienne, Jean-Paul
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Le, Amanda T.
• Application Number:
  US08/324,609
• Time in Patent Office: 910 Days
• Field of Search: 375/371, 375/372, 375/354, 365/189.01, 365/189.04, 365/189.05, 365/206, 370/100.1, 370/101, 370/102, 370/105.1, 370/105.3, 370/108, 370/84, 370/110.1, 370/111
• US Class Current: 375/372
• CPC Class Codes: H04J 3/076 Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking

Abstract

A digital bit stream from a first synchronous link is timed by a first clock and is to be sent over a second synchronous link timed by a second clock. A device for justifying the bit stream at regular intervals includes a buffer memory. Respective pointers supply buffer memory write and read addresses. A value indicating how full the buffer memory is is calculated and compared to first and second threshold values to produce a justification command signal. The first and second variable threshold values are determined according to the phase difference between the header of a row received from the first link and the header of a row sent at the same time on the second link. The device finds an application in gateways at the input of and in telecommunication networks using the synchronous digital hierarchy.

Claims

1. A device for justifying at regular intervals a digital bit stream received from a first synchronous link timed by a first clock and to be sent on a second synchronous link timed by a second clock, said digital bit stream comprising a continuous sequence of rows of bits, each row comprising a fixed total number of bits but including a payload comprising a variable number of bits and a header comprising a variable number of bits, the numbers of bits varying according to whether said row has been subjected to positive justification, negative justification or no justification, the device including:

a buffer memory into which said payload is written under the control of said first clock and from which said payload is read under the control of said second clock;

means for calculating a filling value indicative of how full said buffer memory is;

means for comparing said filling value to first and second variable threshold values to produce a negative justification command signal when it is greater than said first threshold value and to produce a positive justification command signal when it is less than said second threshold value; and

means for determining the first and second variable threshold values according to the phase difference between the header of a row received from said first link and the header of a row sent on said second link.

2. A device according to claim 1, wherein said means for determining said first and second threshold values include:

means for supplying a value representing the phase difference between the header of a row received and the header of a row sent; and

two first function generators operating under the control of said value representing said phase difference and supplying respective threshold values.

3. A device according to claim 2, wherein each of said two function generators generates a sawtooth function and a first slope of the sawtooth corresponds to a first time interval in which said phase difference between the header of a row received and the header of a row sent is such that the latter header has a phase delay relative to the former header and the two headers overlap in time, and a second slope of the sawtooth corresponds to a second time interval in which the above two conditions are not satisfied simultaneously.

4. A device according to claim 1, wherein said means for determining said first and second variable threshold values are also responsive to a justification indicator signal indicating whether a row has been subjected to justification or not.

5. A device according to claim 4, wherein said means for determining said first and second threshold values include:

a counter supplying a value representing said phase difference between the header of a row received and the header of a row sent;

two first function generators operating under the control of said value representing said phase difference and supplying respective values;

a high-pass digital filter for filtering said justification indicator signals;

two second function generators operating under the control of the filtered signal and supplying respective values; and

means for calculating said first and second threshold values by respectively adding a value supplied by said first function generators and a value supplied by said second function generators.

6. A device according to claim 5, wherein said digital filter is a variable bandwidth high-pass filter in which the bandwidth is determined by the value of at least one parameter, the device including means for determining the value of each filter parameter according to how full said buffer memory is, in order to increase the bandwidth of said filter if a transient tends to saturate said buffer memory.

7. A device according to claim 6, wherein said means for determining the value of at least one parameter modify the value of at least one parameter in a direction to increase said bandwidth if said memory is full to above a predetermined threshold, and in synchronism with justification, in order to modify the value of said parameter just before a justification and modify the value of at least one parameter in a direction to reduce said bandwidth:

if the buffer becomes full to less than a predetermined threshold value; and

if the above condition is satisfied for a predetermined time; and

if they detect a series of justifications with no interruption during said predetermined time.

8. A device according to claim 6, wherein the bandwidth of said filter is determined by at least two parameters and said means for determining the value of each filter parameter compare said filling value to a plurality of separate fixed threshold values and modify only one parameter at a time when said filling value becomes respectively greater than or less than a threshold value.

9. A device according to claim 6, wherein said filter includes at least two stages and the final value supplied by a first stage is respectively multiplied or divided by two when the value of a parameter is increased or decreased by one unit, and wherein said first stage further includes means for multiplying or dividing by 2^k the value supplied by said first stage according to whether said means for determining the value of each filter parameter determine for said first stage a parameter modification equal to +k or -k, respectively, where k is a non-null integer.

10. A device according to claim 5, wherein said justification indicator signal temporarily assumes values of opposite sign to indicate positive justification and negative justification, respectively, and assumes a null value in the absence of any justification, and said second function generators respectively generate the following functions:

a function increasing linearly with the filtered justification signal when the latter indicates positive justification and having a predetermined fixed value when it indicates negative justification or no justification; and

a function increasing linearly with the filtered justification signal when the latter indicates negative justification and having a predetermined fixed value when it indicates positive justification or no justification.