Integrated circuit that performs multiple communication tasks

• US 5,621,800 A
• Filed: 11/01/1994
• Issued: 04/15/1997
• Est. Priority Date: 11/01/1994
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Corleto, Jose G., Astrachan, Paul M., Anderson, Donald C., Weng, Chia-Shiann, Kuenast, Walter U., Curtis, Peter C.
• Primary Examiner(s): CANGIALOSI, SALVATORE A
• Application Number:
  US08/333,152
• Time in Patent Office: 896 Days
• Field of Search: 380/49, 364/131, 364/133, 364/134, 395/163
• US Class Current: 380/266
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04B 1/406 with more than one transmission mode, e.g. analog and digital modes
• CPC Class Codes: H04M 9/082 using echo cancellers echo cancellers per se H04B3/23

Abstract

An integrated circuit that provides multiple communication functions is accomplished by providing an integrated circuit (24) that includes memory (70) which stores an audio code algorithm, echo cancellation information, a modem processing algorithm, and audio data. The memory (70) is coupled via a data bus (50) to a signal converter (56), a central processing unit (58), and a first co-processor (72). The signal converter (56) provides an analog-to-digital input port (78) and a digital-to-analog output port (80) for the integrated circuit (24), wherein the audio data is received via the analog-to-digital input port (78). The central processing unit (58) executes at least a first portion of the audio coding algorithm upon the audio data and executes a first portion of the modem processing algorithm, while the first co-processor (72) executes an echo cancellation algorithm.

Claims

1. An integrated circuit comprising:

a memory that stores an audio coding algorithm, echo cancellation information, a modem processing algorithm, and audio data;

a signal converter operably coupled to the memory, wherein the signal converter provides an analog-to-digital input port and a digital-to-analog, output port for the integrated circuit, and wherein the analog-to-digital input port provides the audio data to the memory;

a central processing unit operably coupled to the memory via a first information bus, and has access to the entire memory, wherein the central processing unit executes at least a first portion of the audio coding algorithm upon the audio data and executes at least a first portion of the modem processing algorithm; and

a first co-processor operably coupled to only a portion of the memory, via a second information bus, the portion of the memory is used for storing the echo cancellation information, the first co-processor is coupled to the central processing unit, wherein the first co-processor contains an echo cancellation algorithm and performs, utilizing the echo cancellation information, the echo cancellation algorithm upon the audio data under control of the central processing unit.

2. The integrated circuit of claim 1, wherein the central processing unit controls execution of the echo cancellation algorithm by the first co-processor by providing control signals to the first co-processor via a control bus.

3. The integrated circuit of claim 1, wherein the first co-processor further stores a second portion of the audio coding algorithm and executes the second portion of the audio coding algorithm under control and in cooperation with the central processing unit.

4. The integrated circuit of claim 3, wherein the first portion of the audio coding algorithm comprises an audio compression algorithm and the second portion of the audio coding algorithm comprises a lag search algorithm.

5. The integrated circuit of claim 1 further comprises a second co-processor operably coupled to the central processing unit and the memory, wherein the second co-processor executes, under control of the central processing unit, a third portion of the audio processing algorithm.

6. The integrated circuit of claim 5, wherein the memory further stores a user tone generation algorithm, and wherein, the second co-processor executes the user tone generation algorithm as the third portion of the audio processing algorithm.

7. The integrated circuit of claim 1 further comprises a third co-processor operably coupled to the memory and the central processing unit, wherein the third co-processor executes, under control of the central processing unit, a second portion of the modem processing algorithm.

8. The integrated circuit of claim 7, wherein the third co-processor executes an encryption algorithm as the second portion of the modem processing algorithm.

9. The integrated circuit of claim 1 further comprises a fourth co-processor operably coupled to the central processing unit, wherein the fourth co-processor executes, under control of the central processing unit, a third portion of the modem processing algorithm.

10. The integrated circuit of claim 9, wherein the third portion of the modem processing algorithm comprises an equalization algorithm.

11. The integrated circuit of claim 1 further comprises a modulation signal converter operably coupled to the memory, wherein the modulation signal converter receives first band analog data and converts the first band analog data to first digital data, and wherein the first digital data is stored in memory as at least part of the audio data.

12. The integrated circuit of claim 1, wherein the modulation signal converter is operably coupled to the central processing unit, wherein the modulation signal converter converts second digital data to second band analog signals.

13. The integrated circuit of claim 1 further comprises a digital data interface operably coupled to the central processing unit, wherein the digital data interface provides an input/output path for data transmissions.

14. An integrated circuit comprising:

a memory that stores an audio coding algorithm, a modem processing algorithm, audio data, and transmit data;

a signal converter operably coupled to the memory, wherein the signal converter provides an analog-to-digital input port and wherein the analog-to-digital input port provides audio data to the memory;

a central processing unit operably coupled to the memory via a first information bus, wherein the central processing unit executes at least a first portion of the audio coding algorithm and at least a first portion of the modem processing algorithm upon the audio data to produce the transmit data;

a first co-processor operably coupled to only a portion of the memory, via a second information bus, the portion of the memory is used for storing echo cancellation information, the first co-processor is coupled to the central processing unit, wherein the first co-processor contains an echo cancellation algorithm and performs, utilizing the echo cancellation information, the echo cancellation algorithm upon the audio data tinder control of the central processing unit;

a modulation signal converter operably coupled to the memory, wherein the modulation signal converter receives first band analog data and converts the first band analog data to first digital data, and receives second digital data and converts the second digital data to a second band analog output; and

a digital modulator operably coupled to the modulation signal converter and the memory, wherein the digital modulator produces the second digital data based on the transmit data and provides the second digital data to the modulation signal converter.

15. The integrated circuit of claim 14, wherein the central processing unit further executes at least a first portion of an audio decoding algorithm upon the first digital data to produce digital audio information.

16. The integrated circuit of claim 15, wherein the signal converter further comprises a digital-to-analog output port for the integrated circuit, and wherein the digital-to-analog output port converts the digital audio information into output audio data.

17. An integrated circuit for performing multiple communications tasks, comprising:

a memory that stores audio information including echo cancellation information and tone generation data;

a central processing unit, operably coupled to the memory via a first information bus, the central processing unit having access to all of the memory;

a first co-processor operably coupled to only a portion of the memory, via a second information bus, the portion of the memory being used for storing the echo cancellation information, the first co-processor is coupled to the central processing unit, wherein the first co-processor contains an echo cancellation algorithm and performs, utilizing the echo cancellation information, the echo cancellation algorithm upon the audio data under control of the central processing unit;

a second co-processor operably coupled to the central processing unit and to the memory, wherein the second co-processor executes, under control of the central processing unit, a user tone generation algorithm using the tone generation data;

a third co-processor operably coupled to the memory and the central processing unit, wherein the third co-processor executes, under control of the central processing unit, art encryption algorithm; and

a fourth co-processor operably coupled to the central processing unit, wherein the fourth co-processor executes, under control of the central processing unit, an equalization algorithm.

18. The integrated circuit of claim 17 further comprises a command parser that provides an auxiliary audio/data command signal to a channel encoder and a channel decoder, the channel decoder operably coupled to the fourth co-processor, wherein the channel decoder converts an equalized data stream into decoded audio information, wherein the auxiliary audio/data command signal indicates whether the integrated circuit is processing auxiliary input data, auxiliary output data, auxiliary input audio, or auxiliary output audio.

19. The integrated circuit of claim 18 further comprises an auxiliary interface operably coupled to a channel encoder and the command parser, wherein the auxiliary interface receives input data and provides the input data as the auxiliary input data to the channel encoder, such that the auxiliary input data is converted to second band data.

20. The integrated circuit of claim 18 further comprises an auxiliary interface operably coupled to the channel decoder and the command parser, wherein the auxiliary interface receives the auxiliary output data from the channel decoder and provides the auxiliary output data as output data.

21. The integrated circuit of claim 18 further comprises an auxiliary interface operably coupled to the first co-processor and the command parser, wherein the auxiliary interface provides the auxiliary input audio to the first co-processor, such that the auxiliary input audio is converted to second band data.

22. The integrated circuit of claim 18 further comprises an auxiliary interface operably coupled to the first co-processor and the command parser, wherein the auxiliary interface receives the auxiliary output audio from the first co-processor.

23. The integrated circuit of claim 18, wherein the fourth co-processor further comprises an equalizer comprising a match filter, a soft decision element, and an add-compare-select element interoperbly coupled to provide an equalized data stream to the channel decoder.

24. The integrated circuit of claim 23, wherein the channel decoder comprises a de-interleave element, a block decode element, a cycle redundancy check element, and a receive quality element interoperably coupled to convert the equalized data stream into decoded audio information.

25. The integrated circuit of claim 24, wherein the first co-processor comprises a voice coding element that converts the decoded audio information into first digitized audio data.

26. The integrated circuit of claim 25, wherein the second co-processor comprises a speech encoder that converts second digitized audio data into the processed audio information.

27. The integrated circuit of claim 26, wherein the first co-processor further comprises a lag search element operably coupled to the speech encoder to convert the second digitized audio data into the processed audio information.

28. The integrated circuit of claim 19, wherein the channel encoder comprises a block encode element and an interleave element interoperably coupled to convert processed audio information into an encoded data stream.

29. The integrated circuit of claim 23 further comprises and encryption element and a decryption element, wherein the decryption element is operably coupled to the equalizer and the channel decoder and the encryption element is operably coupled to the channel encoder and a digital signal modulator.

30. A method for performing multiple communication tasks by an integrated circuit, the method comprising the steps of:

receiving first band data;

converting the first band data into first digital data using a modulation signal converter;

equalizing the first digital data into an equalized data stream;

decoding the equalized data stream into decoded information using a first audio processor;

processing the decoded information into first digitized audio data using the first audio processor;

converting the first digitized audio data into an analog audio signal using a signal converter;

converting an input analog signal into second digitized audio data using the signal converter;

processing the second digitized audio data and performing echo-cancellation on the second digitized audio data to produce processed audio information using a second audio processor, the second audio processor only having access to a portion of a memory for storing the second digitized audio data via a dedicated bus;

encoding the processed audio information into an encoded data stream using a third audio processor;

converting the encoded data stream into second digital data using a digital modular; and

converting second digital data into second band data using the modulation signal converter.

31. The method of claim 30 further comprises receiving an auxiliary audio/data signal, wherein the auxiliary audio/data command indicates whether the integrated circuit is processing auxiliary input data, auxiliary output data, auxiliary input audio, or auxiliary output audio.

32. The method of claim 31 further comprises, when the auxiliary audio/data signal indicates the auxiliary input data,

receiving input data;

providing the input data as the auxiliary input data; and

encoding, at the step of encoding, the auxiliary input data into the encoded data stream.

33. The method of claim 31 further comprises, when the auxiliary audio/data signal indicates the auxiliary output data,

providing, after the step of decoding the equalized data stream into decoded audio information, the decoded audio information as the auxiliary output data.

34. The method of claim 31 further comprises, when the auxiliary audio/data signal indicates the auxiliary input audio,

receiving, prior to the step of processing the second digitized audio data, the auxiliary input audio;

and

processing the auxiliary input audio as the second digitized audio data to produce the processed audio information.

35. The method of claim 31 further comprises, when the auxiliary audio/data signal indicates the auxiliary output audio, providing, after the step of processing the decoded audio information into first digitized audio data;

the first digitized audio data as the auxiliary output audio.

36. The method of claim 30, wherein the step of equalizing the first digital data into an equalized data stream comprises:

filtering the first digital data to produce filtered data;

interpreting the filtered data to determine most probable data; and

performing an add-compare-select function on the most probable data to produce the equalized data stream.

37. The method of claim 30, wherein the step of decoding the equalized data stream into decoded audio information comprises:

de-interleaving the equalized data stream to produce de-interleaved data;

block decoding the de-interleaved data to produce block decoded data;

performing a cycle redundancy check on the block decoded data to produced checked data; and

performing receive quality operation on the checked data to produce the decoded audio information.

38. The method of claim 30, wherein the step of processing the second digitized audio data into processed audio information comprises:

performing a lag search operation on the second digitized audio data to produce pitch data;

performing an echo cancellation operation on the second digitized audio data to produce echo cancelled data; and

performing a speech encode operation on the echo cancelled data utilizing the pitch data to produce the processed audio information.

39. The method of claim 30, wherein the step of encoding the processed audio information into encoded data stream comprises:

block encoding the processed audio information to produce block encoded data; and

interleaving the block encoded data to produce the encoded data stream.

40. The method of claim 30 further comprises, prior to the step of converting the encoded data stream into second digital data,

encrypting the encoded data stream to produce an encrypted data stream;

and

converting the encrypted data stream into the second digital data.

41. The method of claim 30 further comprises, prior to the step of decoding the equalized data stream into decoded audio information,

decrypting the equalized data stream to produce decrypted data;

and

decoding the decrypted data to produce the decoded audio information.