Method and apparatus for serial bus elements of an hierarchical serial bus assembly to electrically represent data and control states to each other

• US 5,621,901 A
• Filed: 10/31/1994
• Issued: 04/15/1997
• Est. Priority Date: 10/31/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Volk, Andrew M., Morriss, Jeff C.
• Primary Examiner(s): Sheikh, Ayaz R.
• Application Number:
  US08/332,337
• Time in Patent Office: 897 Days
• Field of Search: 395/306, 395/200.13, 341/143
• US Class Current: 710/305
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission

Abstract

Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical bus assembly for electrically representing data and control states each other. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. The serial bus elements are interconnected to each other using low cost two wire signal cable. Electrical signals are propagated between the serial bus elements in a differential manner. These circuitry and complementary logic of the serial bus elements jointly implement inference of data and control states from the states and/or durations of the propagating electrical signals.

Claims

1. An apparatus for incorporation into a first and a second serial bus element of a serial bus assembly having a plurality of serial bus elements, to allow the two serial bus elements to electrically represent data and control states to each other, said apparatus comprising:

first driver means for incorporation into the first serial bus element for driving a first pair of electrical signals in selected ones of voltage states for selected ones of time durations in a differential manner over a first pair of signal wires disposed in a first cable interconnecting the first and second serial bus elements;

encoding means for incorporation into the first serial bus element and coupled to the first driver means for controlling the first driver means thereby encoding data and control states in the first pair of electrical signals;

second driver means for incorporation into the second serial bus elements for receiving the first pair of electrical signals, and in response, outputting difference signals; and

decoding means for incorporation into the second serial bus elements and coupled to the second driver means for receiving and decoding the difference signals.

2. The apparatus as set forth in claim 1, wherein said encoding means encodes a logical one by causing said first driver means to drive the first pair of electrical signals with a positive difference greater than a predetermined positive voltage threshold.

3. The apparatus as set forth in claim 1, wherein said encoding means encodes a logical zero by causing said first driver means to drive the first pair of electrical signals with a negative difference that is more negative than a predetermined negative voltage threshold.

4. The apparatus as set forth in claim 1, wherein, said encoding means encodes a "connected" state by causing said first driver means to drive the first pair of electrical signals simultaneously greater than a predetermined single ended voltage (V_se0) for a predetermined duration.

5. The apparatus as set forth in claim 1, wherein, said encoding means encodes a "disconnected" state by causing said first driver means to drive the first pair of electrical signals simultaneously smaller than a predetermined single ended voltage (V_se0) for a predetermined duration.

6. The apparatus as set forth in claim 1, wherein, said encoding means encodes a start of packet demarcation by causing said first driver means to drive the first pair of electrical signals simultaneously smaller than a predetermined single ended voltage (V_se0) for a predetermined duration.

7. The apparatus as set forth in claim 1, wherein, said encoding means encodes an end of packet demarcation by causing said first driver means to drive the first pair of electrical signals simultaneously smaller than a predetermined single ended voltage (V_se0) for a predetermined duration.

8. The apparatus as set forth in claim 1, wherein,

said encoding means encodes a "connected" state by causing said first driver means to drive the first pair of electrical signals simultaneously greater than a predetermined single ended voltage (V_se0) for a first predetermined duration;

and

said encoding means encodes a "disconnected" state by causing said first driver means to drive the first pair of electrical signals simultaneously smaller than the predetermined single ended voltage (V_se0) for the first predetermined duration.

9. The apparatus as set forth in claim 8, wherein,

said encoding means encodes a start of packet demarcation by causing said first driver means to drive the first pair of electrical signals simultaneously smaller than the predetermined single ended voltage (V_se0) for a second predetermined duration, the second predetermined duration being shorter than the first predetermined duration;

and

said encoding means encodes an end of packet demarcation by causing said first driver means to drive the first pair of electrical signals simultaneously smaller than the predetermined single ended voltage (V_se0) for a third predetermined duration, the third predetermined duration being shorter than the second predetermined duration.

10. In a computer system comprising a serial bus assembly having a plurality of serial bus elements, a method for the serial bus elements to electrically represent data and control states to each other, said method comprising the steps of:

a) driving a first pair of electrical signals in selected ones of voltage states for selected ones of time durations in a differential manner over a first pair of signal wires disposed in a first cable interconnecting a first and a second serial bus element by the first serial bus element;

b) controlling the electrical signal driving performed in step (a) to encode data and control states in the first pair of electrical signals by the first serial bus element;

c) receiving the first pair of electrical signals, and in response, outputting difference signals, by the second serial bus element; and

d) decoding the difference signals by the second serial bus element.

11. The method as set forth in claim 10, wherein step (a) comprises driving the first pair of electrical signals with a positive difference greater than a predetermined positive voltage threshold by the first serial bus element to represent a logical one value, and driving the first pair of electrical signals with a negative difference that is more negative than a predetermined negative voltage threshold by the first serial bus element to represent a logical zero value.

12. The method as set forth in claim 11, wherein, step (a) comprises driving the first pair of electrical signals simultaneously greater than a predetermined single ended voltage (V_se0) for a first predetermined duration by the first serial bus element to represent a "connected" state, and driving the first pair of electrical signals simultaneously smaller than the predetermined single ended voltage (V_se0) for the first predetermined duration by the first serial bus element to represent a "disconnected" state.

13. The method as set forth in claim 12, wherein, step (a) comprises driving the first pair of electrical signals simultaneously smaller than the predetermined single ended voltage (V_se0) for a second predetermined duration by the first serial bus element to represent a start of packet demarcation, the second predetermined duration being shorter than the first predetermined duration, and driving the first pair of electrical signals simultaneously smaller than the predetermined single ended voltage (V_se0) for a third predetermined duration by the first serial bus element to represent an end of packet demarcation, the third predetermined duration being shorter than the second predetermined duration.

14. A bus controller for incorporation into a serial bus assembly having at least one other serial bus element, the bus controller comprising:

first driver means for driving a first pair of electrical signals in selected ones of voltage states for selected ones of time durations in a differential manner over a first pair of signal wires disposed in a first cable interconnecting the bus controller to a first of the at least one other serial bus element;

encoding means coupled to the first driver means for controlling the first driver means thereby encoding data and control states in the first pair of electrical signals;

second driver means for receiving a second pair of electrical signals in selected ones of the voltage states for selected ones of the time durations also in a differential manner over the first pair of signal wires from the first of the at least one other bus element, and in response, outputting difference signals; and

decoding means coupled to the second driver means for receiving and decoding the difference signals.

15. The bus controller as set forth in claim 14, wherein

said encoding means encodes a logical one by causing said first driver means to drive the first pair of electrical signals with a positive difference greater than a predetermined positive voltage threshold;

and

said encoding means encodes a logical zero by causing said first driver means to drive the first pair of electrical signals with a negative difference that is more negative than a predetermined negative voltage threshold.

16. The bus controller as set forth in claim 14, wherein,

said encoding means encodes a "connected" state by causing said first driver means to drive the first pair of electrical signals simultaneously greater than a predetermined single ended voltage (V_se0) for a first predetermined duration;

and

said encoding means encodes a "disconnected" state by causing said first driver means to drive the first pair of electrical signals simultaneously smaller than the predetermined single ended voltage (V_se0) for the first predetermined duration.

17. The bus controller as set forth in claim 16, wherein,

said encoding means encodes a start of packet demarcation by causing said first driver means to drive the first pair of electrical signals simultaneously smaller than the predetermined single ended voltage (V_se0) for a second predetermined duration, the second predetermined duration being shorter than the first predetermined duration;

and

said encoding means encodes an end of packet demarcation by causing said first driver means to drive the first pair of electrical signals simultaneously smaller than the predetermined single ended voltage (V_se0) for a third predetermined duration, the third predetermined duration being shorter than the second predetermined duration.

18. A bus signal distributor for incorporation into a serial bus assembly having at least one other bus element, the bus signal distributor comprising:

first driver means for driving a first pair of electrical signals in selected ones of voltage states for selected ones of time durations in a differential manner over a first pair of signal wires disposed in a first cable interconnecting the bus signal distributor to a first of the at least one other bus element;

encoding means coupled to the first driver means for controlling the first driver means thereby encoding data and control states in the first pair of electrical signals;

second driver means for receiving a second pair of electrical signals in selected ones of the voltage states for selected ones of the time durations also in a differential manner over the first pair of signal wires from the first of the at least one other bus element, and in response, outputting difference signals; and

decoding means coupled to the second driver means for receiving and decoding the difference signals.

19. The bus signal distributor as set forth in claim 18, wherein

said encoding means encodes a logical one by causing said first driver means to drive the first pair of electrical signals with a positive difference greater than a predetermined positive voltage threshold;

and

said encoding means encodes a logical zero by causing said first driver means to drive the first pair of electrical signals with a negative difference that is more negative than a predetermined negative voltage threshold.

20. The bus signal distributor as set forth in claim 18, wherein,

said encoding means encodes a "connected" state by causing said first driver means to drive the first pair of electrical signals simultaneously greater than a predetermined single ended voltage (V_se0) for a first predetermined duration;

and

said encoding means encodes a "disconnected" state by causing said first driver means to drive the first pair of electrical signals simultaneously smaller than the predetermined single ended voltage (V_se0) for the first predetermined duration.

21. The bus signal distributor as set forth in claim 20, wherein,

said encoding means encodes a start of packet demarcation by causing said first driver means to drive the first pair of electrical signals simultaneously smaller than the predetermined single ended voltage (V_se0) for a second predetermined duration, the second predetermined duration being shorter than the first predetermined duration;

and

said encoding means encodes an end of packet demarcation by causing said first driver means to drive the first pair of electrical signals simultaneously smaller than the predetermined single ended voltage (V_se0) for a third predetermined duration, the third predetermined duration being shorter than the second predetermined duration.

22. A bus interface for incorporation into a serial bus assembly having at least one other serial bus element, the bus interface comprising:

first driver means for driving a first pair of electrical signals in selected ones of voltage states for selected ones of time durations in a differential manner over a first pair of signal wires disposed in a first cable interconnecting the bus interface to the first of the at least one other serial bus element;

encoding means coupled to the first driver means for controlling the first driver means thereby encoding data and control states in the first pair of electrical signals;

second driver means for receiving a second pair of electrical signals in selected ones of the voltage states for selected ones of the time durations also in a differential manner over the first pair of signal wires from the first of the at least one other serial bus element, and in response, outputting difference signals; and

decoding means coupled to the second driver means for receiving and decoding the difference signals.

23. The bus interface as set forth in claim 22, wherein

said encoding means encodes a logical one by causing said first driver means to drive the first pair of electrical signals with a positive difference greater than a predetermined positive voltage threshold;

and

said encoding means encodes a logical zero by causing said first driver means to drive the first pair of electrical signals with a negative difference that is more negative than a predetermined negative voltage threshold.

24. The bus interface as set forth in claim 22, wherein,

said encoding means encodes a "connected" state by causing said first driver means to drive the first pair of electrical signals simultaneously greater than a predetermined single ended voltage (V_se0) for a first predetermined duration;

and

said encoding means encodes a "disconnected" state by causing said first driver means to drive the first pair of electrical signals simultaneously smaller than the predetermined single ended voltage (V_se0) for the first predetermined duration.

25. The bus interface as set forth in claim 24, wherein,

said encoding means encodes a start of packet demarcation by causing said first driver means to drive the first pair of electrical signals simultaneously smaller than the predetermined single ended voltage (V_se0) for a second predetermined duration, the second predetermined duration being shorter than the first predetermined duration;

and

said encoding means encodes an end of packet demarcation by causing said first driver means to drive the first pair of electrical signals simultaneously smaller than the predetermined single ended voltage (V_se0) for a third predetermined duration, the third predetermined duration being shorter than the second predetermined duration.