Clock system

• US 5,623,234 A
• Filed: 03/04/1996
• Issued: 04/22/1997
• Est. Priority Date: 03/04/1996
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Gandal, Stefania, Einav, Alick, Shaik, Yehuda, Kurnick, Moti
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Luu, An T.
• Application Number:
  US08/610,503
• Time in Patent Office: 414 Days
• Field of Search: 331/49, 331/46, 307/64, 307/85, 307/86, 307/87, 327/292
• US Class Current: 331/49
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence

Abstract

A clock system (2) for providing a system clock signal at a clock output (4) for use by a processing unit comprises a first oscillator circuit (6) which is enabled in response to a wake up signal provided by the processing unit to provide a first clock signal (RINGO CLOCK) at an output, and a second oscillator circuit (8) comprising a PLL (14) and an oscillator (16). The second oscillator (8) circuit provides a second clock signal (PLL CLOCK) and a lock signal (LOCKED) at first and second outputs respectively when the PLL is locked. The clock system (2) further comprises control circuitry (10) coupled to the output of the first oscillator circuit (6) and to the first and second outputs of the second oscillator circuit (8) for coupling the first clock signal (RINGO CLOCK) to the clock output (4) to provide the system clock signal or when the control circuitry (10) receives the lock signal (LOCKED) for coupling the second clock signal (PLL CLOCK) and not the first clock signal (RINGO CLOCK) to the clock output (4) to provide the system clock signal.

Claims

1. A clock system for providing a system clock signal at a clock output, when enabled, for use by a processing unit, the clock system being enabled in response to a wake up signal provided by the processing unit, the clock system comprising:

first oscillator circuit being enabled in response to the wake up signal to provide a first clock signal at an output;

second oscillator circuit comprising a PLL and an oscillator, the second oscillator circuit when enabled providing a second clock signal and a lock signal at first and second outputs respectively when the PLL is locked;

control circuitry coupled to the output of the first oscillator circuit and to the first and second outputs of the second oscillator circuit for coupling the first clock signal to the clock output to provide the system clock signal or for coupling the second clock signal and not the first clock signal to the clock output to provide the system clock signal when the control circuitry receives the lock signal.

2. A clock system according to claim 1 wherein the second oscillator circuit is enabled in response to the wake up signal, and wherein the second oscillator circuit provides the lock signal a predetermined time after the second oscillator circuit is enabled.

3. A clock system according to claim 1 wherein the first oscillator circuit is disabled in response to a power down signal generated by the processing unit before the second oscillator circuit is enabled whereby the clock system is disabled and no system clock signal is generated.

4. A clock system according to claim 1 wherein the second oscillator circuit is enabled in response to a signal generated by the processing unit after the wake up signal, and wherein the second oscillator circuit provides the lock signal a predetermined time after the second oscillator circuit is enabled.

5. A clock system according to claim 1 wherein the first oscillator circuit is disabled in response to the second oscillator circuit generating the lock signal.

6. A clock system according to claim 1 wherein the first oscillator circuit comprises a ring oscillator circuit.

7. A clock system according to claim 6 wherein the ring oscillator circuit comprises an odd number of inverters connected in a ring in series with a resistor and capacitor, and a divider coupled to an output node in the ring to divide the signal at the output node by a multiple of two, the signal at an output of the divider forming the first clock signal, wherein oscillations of the ring oscillator circuit are enabled in response to the wake up signal.