Capacitive load driving circuit including input selection circuit and liquid crystal display device using the driving circuit

• US 5,623,279 A
• Filed: 09/12/1994
• Issued: 04/22/1997
• Est. Priority Date: 09/10/1993
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Itakura, Tetsuro, Shima, Takeshi
• Primary Examiner(s): Bayerl, Raymond J.
• Assistant Examiner(s): LOCKETT, KUNIKI
• Application Number:
  US08/304,544
• Time in Patent Office: 953 Days
• Field of Search: 307/404, 327/94, 330/253, 345/98, 345/99, 345/100, 345/104, 345/95
• US Class Current: 345/98
• CPC Class Codes: G09G 2310/0291 Details of output amplifiers or buffers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

A capacitative load driving circuit is provided in a liquid crystal display device and has an input selection circuit having a wide and effective voltage range of an input signal. The driving circuit changes over through source or emitter followers formed by two types of conductivity, for detecting as to whether or not a potential of the input signal is in an input voltage range of a differential amplifier circuit constituting a voltage follower after selecting at least one input signal through any of source or emitter followers.

Claims

1. A capacitive load driving circuit comprising:

first through n-th input terminals for respectively receiving first through n-th input signals, where n is an integer greater than or equal to two;

first through n-th source followers formed by first through n-th field effect transistors (FET) each having an input terminal which is respectively connected to said first through n-th input terminals and formed of a first conductive type semiconductor;

(n+1)-th through 2n-th source followers formed by (n+1)-th through 2n-th FET each having an input terminal which is respectively connected to said first through n-th input terminals and formed of a second conductive type semiconductor;

a differential amplifier circuit having two pairs of positive inputs and negative inputs, namely, a first positive input, a first negative input, a second positive input and a second negative input, and for operating by a signal supplied to any pair of positive and negative inputs by a control signal;

a (2n+1)-th source follower formed by the first conductive type semiconductor FET and inputting an output of said differential amplifier circuit to said first negative input;

a (2n+2)-th source follower formed by the second conductive type semiconductor FET and inputting said output of said differential amplifier circuit to said second negative input;

first switch means for selecting any of outputs from said first through n-th source followers formed by the first conductive type FET on the basis of a selection signal;

second switch means for selecting any of outputs from said (n+1)-th through 2n-th source followers formed by the second conductive type FET on the basis of said selection signal; and

control signal generation means for generating said control signal on the basis of an operation potential after inputting any of outputs from said first switch means and said second switch means,

wherein said output of said first switch means is supplied to said first positive input of said differential amplifier circuit, said output of said second switch means is supplied to said second positive input of said differential amplifier circuit, said output of said (2n+1)-th source follower is supplied to said first negative input of said differential amplifier circuit, and said output of said (2n+2)-th source follower is supplied to said second negative input of said differential amplifier circuit.

2. A capacitive load driving circuit comprising:

first through n-th input terminals for respectively receiving first through n-th input signals, where n is an integer greater than or equal to two;

first through n-th source followers formed by first through n-th field effect transistors (FET) each having an input terminal which is respectively connected to said first through n-th input terminals and formed of a first conductive type semiconductor;

(n+1)-th through 2n-th source followers formed by (n+1)-th through 2n-th FET each having an input terminal which is respectively connected to said first through n-th input terminals and formed of a second conductive type semiconductor;

a differential amplifier circuit having two pairs of positive inputs and negative inputs, namely, a first positive input, a first negative input, a second positive input and a second negative input, and for operating by a signal supplied to any pair of positive and negative inputs by a control signal;

first through n-th track and hold means for inputting an output of said differential amplifier circuit;

(2n+1)-th through 3n-th source followers formed by the first conductive type semiconductor FET and inputting an output of said first through n-th track and hold means;

(3n+1)-th through 4n-th source followers formed by the second conductive type semiconductor FET and inputting said output of said first through n-th track and hold means;

first switch means for selecting any of outputs from said first through n-th source followers formed by the first conductive type FET on the basis of a selection signal;

second switch means for selecting any of outputs from said (n+1)-th through 2n-th source followers formed by the second conductive type FET on the basis of said selection signal;

third switch means for selecting any of outputs from said (2n+1)-th through 3n-th source followers formed by the first conductive type FET on the basis of said selection signal;

fourth switch means for selecting any of outputs from said (3n+1)-th through 4n source followers formed by the second conductive type FET on the basis of said selection signal and

control signal generation means for generating said control signal on the basis of an operation potential after inputting any of outputs from said first switch means and said second switch means,

wherein an output of said first switch means is supplied to said first positive input of said differential amplifier circuit, an output of said second switch means is supplied to said second positive input of said differential amplifier circuit, an output of said third switch is supplied to said first negative input of said differential amplifier circuit, an output of said fourth switch means is supplied to said second negative input of said differential amplifier circuit, and said first through n-th track and hold means perform tracking and holding on the basis of said selection signal.

3. The capacitive load driving circuit according to claim 2, wherein

said track and hold circuit is comprised of switch means and a capacitance.

4. A capacitive load driving circuit comprising:

first through n-th input terminals for respectively receiving first through n-th input signals, where n is an integer greater than or equal to two;

first through n-th emitter followers formed by first through n-th transistors each having an input terminal which is respectively connected to said first through n-th input terminals and formed of a first conductive type semiconductor;

(n+1)-th through 2n-th through 2n-th emitter followers formed by (n+1)-th through 2n-th transistors each having an input terminal which is respectively connected to said first through n-th input terminals and formed of a second conductive type semiconductor;

a differential amplifier circuit having two pairs of positive inputs and negative inputs, namely, a first positive input, a first negative input, a second positive input and a second negative input, and for operating by a signal supplied to any pair of positive and negative inputs by a control signal;

a(2n+2)-th emitter follower formed by the first conductive type semiconductor and inputting an output of said differential amplifier circuit;

a(2n+2)-th emitter follower formed by the second conductive type semiconductor and inputting said output of said differential amplifier circuit;

first switch means for selecting any of outputs from said first through n-th emitter followers formed by the first conductive type transistor on the basis of a selection signal;

second switch means for selecting any of outputs from said (n+1)-th through 2n-th emitter followers formed by the second conductive type transistor on the basis of said selection signal; and

control signal generation means for generating said control signal on the basis of an operation potential after inputting any of outputs from said first switch means and said second switch means,

wherein said output of said first switch means is supplied to said first positive input of said differential amplifier circuit, said output of said second switch means is supplied to said second positive input of said differential amplifier circuit, said output of said (2n+1)-th emitter follower is supplied to said first negative input of said differential amplifier circuit, and said output of said (2n+2)-th emitter follower is supplied to said second negative input of said differential amplifier circuit.

5. A capacitive load driving circuit comprising:

first through n-th input terminals for respectively receiving first through n-th input signals;

first through n-th emitter followers formed by first through n-th transistors each having an input terminal which is respectively connected to said first through n-th input terminals and formed of a first conductive type semiconductor, where n is an integer greater than or equal to two;

(n+1)-th through 2n-th emitter followers formed by (n+1)-th through 2n-th transistors each having an input terminal which is respectively connected to said first through n-th input terminals and formed of a second conductive type semiconductor;

a differential amplifier circuit having two pairs of positive inputs and negative inputs, namely, a first positive input, a first negative input, a second positive input and a second negative input, and for operating by a signal supplied to any pair of positive and negative inputs by a control signal;

first through n-th track and hold means for inputting an output of said differential amplifier circuit;

(2n+1)-th through 3n-th emitter followers formed by the first conductive type semiconductor transistor and inputting an output of said first through n-th track and hold means;

(3n+1)-th through 4n-th emitter followers formed by the second conductive type semiconductor transistor and inputting said output of said first through n-th track and hold means;

first switch means for selecting any of outputs from said first through n-th emitter followers formed by the first conductive type transistor on the basis of a selection signal;

second switch means for selecting any of outputs from said (n+1)-th through 2n-th emitter followers formed by the second conductive type transistor on the basis of said selection signal;

third switch means for selecting any of outputs from said (2n+1)-th through 3n-th emitter followers formed by the first conductive type transistor on the basis of said selection signal;

fourth switch means for selecting any of outputs from said (3n+1)-th through 4n-th emitter followers formed by the second conductive type transistor on the basis of said selection signal; and

control signal generation means for generating said control signal on the basis of an operation potential after inputting any of outputs from said first switch means and said second switch means,

wherein an output of said first switch mean sis supplied to said first positive input of said differential amplifier circuit, an output of said second switch means is supplied to said second positive input of said differential amplifier circuit, an output of said third switch is supplied to said first negative input of said differential amplifier circuit, an output of said fourth switch means is supplied to said second negative input of said differential amplifier circuit, and said first through n-th track and hold means perform tracking and holding on the basis of said selection signal.

6. The capacitive load driving circuit according to claim 5, wherein

said track and hold circuit is comprised of switch means and capacitance.

7. A liquid crystal display device comprising a plurality of pixels, a liquid crystal display in which signal lines for selectively supplying a video signal to each of said pixels are formed and scanning lines intersecting said signal lines are arranged, first through n-th sample and hold circuits for supplying said video signal to said signal lines after sampling, where n is an integer greater than or equal to two, a capacitive load driving circuit for driving said signal lines after selecting any of outputs of said first through n-th sample and hold circuits, and a selection circuit for selecting any of said scanning lines,

where said capacitive load driving circuit comprises;

first through n-th input terminals for respectively receiving first through n-th input signals;

first through n-th source followers formed by first through n-th field effect transistors (FET) each having an input terminal which is respectively connected to said first through n-th input terminals and formed of a first conductive type semiconductor;

(n+1)-th through 2n-th source followers formed by (n+1)-th through 2n-th FET each having an input terminal which is respectively connected to said first through n-th input terminals and formed of a second conductive type semiconductor;

a differential amplifier circuit having two pairs of positive inputs and negative inputs, namely, a first positive input, a first negative input, a second positive input and a second negative input, and for operating by a signal supplied to any pair of positive and negative inputs by a control signal;

a (2n+1)-th source follower formed by the first conductive type semiconductor FET and inputting an output of said differential amplifier circuit;

a (2n+2)-th source follower formed by the second conductive type semiconductor FET and inputting said output of said differential amplifier circuit;

first switch means for selecting any of outputs from said first through n-th source followers formed by the first conductive type FET on the basis of a selection signal;

second switch means for selecting any of outputs from said (n+1)-th through 2n-th source followers formed by the second conductive type FET on the basis of said selection signal; and

control signal generation means for generating said control signal on the basis of an operation potential after inputting any of outputs from said first switch means and said second switch means,

wherein said output of said first switch means is supplied to said first positive input of said differential amplifier circuit, said output of said second switch means is supplied to said second positive input of said differential amplifier circuit, said output of said (2n+1)-th source follower is supplied to said first negative input of said differential amplifier circuit, and said output of said (2n+2)-th source follower is supplied to said second negative input of said differential amplifier circuit.