Method and apparatus to distribute spare cells within a standard cell region of an integrated circuit

• US 5,623,420 A
• Filed: 11/16/1994
• Issued: 04/22/1997
• Est. Priority Date: 11/16/1994
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Aji, Sandeep, Rusu, Stefan, Yee, Clayton L.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): FREJD, RUSSELL WARREN
• Application Number:
  US08/340,706
• Time in Patent Office: 888 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/468
• US Class Current: 716/120
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

A method and apparatus to distribute spare cells into a standard cell region of an integrated circuit is described. An initial layout of standard cells is first generated by a place and route tool. Afterwards, the initial layout is processed by a spare cell distribution mechanism that simultaneously processes a directive file. The spare cell distribution mechanism distributes, according to a predefined criteria, a preselected cluster of spare cells within the initial layout of standard cells. This processing results in an optimal distribution of spare standard cells within the standard cell region of the semiconductor. The spare cell distribution mechanism also inserts vertical wire terminators into the standard cell region to promote vertical routing, and thus shorter routing paths. In addition, the spare cell distribution mechanism inserts ground connectors and power connectors in the standard cell region to generate a ground and power paths. The outputs of the inserted spare cells may be connected to the ground and power paths until they are subsequently re-routed to correct logic defects in the standard cell region.

Claims

1. A method of inserting standard cells into an integrated circuit, said method comprising the steps of:

generating an initial layout of standard cells in an integrated circuit;

selecting a cluster of standard cell groups to be inserted into said initial layout of standard cells; and

distributing said cluster of standard cell groups into said initial layout of standard cells by repeatedly inserting standard cell groups from said cluster into said initial layout of standard cells.

2. The method of claim 1 wherein said distributing step includes the step of distributing said cluster of standard cell groups in accordance with predetermined criteria based upon the number of tracks in said initial layout of standard cells.

3. The method of claim 1 wherein said distributing step includes the step of distributing said cluster of standard cell groups in accordance with predetermined criteria based upon the power consumption of cells in said cluster.

4. The method of claim 1 wherein said distributing step includes the step of distributing said cluster of standard cell groups in accordance with predetermined criteria based upon the logical function of cells in said cluster.

5. The method of claim 1 further comprising the step of inserting a first spare cell connector and a second spare cell connector in said initial layout of standard cells to force the routing of a track between said first spare cell and said second spare cell.

6. The method of claim 5 wherein said inserting step includes the step of inserting a first power connector and a second power connector in said initial layout of standard cells to force the routing of a horizontal routing track between said first power connector and said second power connector.

7. The method of claim 1 further comprising the step of inserting a spare terminator in said initial layout of standard cells to force the routing of a vertical track between said spare terminator and a standard cell.

8. An apparatus for automatically inserting standard cells into an integrated circuit layout, said apparatus comprising:

a place and route tool to generate an initial layout of standard cells in an integrated circuit; and

a spare cell distribution mechanism to repeatedly insert groups of standard cells from a cluster of standard cells into said initial layout of standard cells.

9. The apparatus of claim 8 wherein said spare cell distribution mechanism distributes said groups of standard cells into said initial layout of standard cells in accordance with predetermined criteria based upon the number of tracks in said initial layout of standard cells.

10. The apparatus of claim 8 wherein said spare cell distribution mechanism distributes said groups of standard cells into said initial layout of standard cells in accordance with predetermined criteria based upon the power consumption of cells in said groups of standard cells.

11. The apparatus of claim 8 wherein said spare cell distribution mechanism distributes said groups of standard cells into said initial layout of standard cells in accordance with predetermined criteria based upon the logical function of cells in said groups of standard cells.

12. The apparatus of claim 8 wherein said spare cell distribution mechanism distributes a spare terminator in said initial layout of standard cells to force the routing of a vertical track between said spare terminator and a standard cell.

13. The apparatus of claim 8 wherein said spare cell distribution mechanism distributes a first spare cell connector at one side of said initial layout of standard cells and a second spare cell connector at a second side of said initial layout of standard cells to force the routing, by said place and route tool, of an additional routing track between said first spare cell connector and said second spare cell connector.

14. The apparatus of claim 13 wherein said first spare cell connector is a first power connector and said second spare cell connector is a second power connector.

15. The apparatus of claim 13 wherein said first spare cell connector is a first ground connector and said second spare cell connector is a second ground connector.