System and method for accessing embedded channels

• US 5,623,480 A
• Filed: 05/26/1995
• Issued: 04/22/1997
• Est. Priority Date: 04/02/1992
• Status: Expired due to Term

• Current Assignee: JDS Uniphase Corporation (Lumentum Holdings Inc.)
• Original Assignee: Applied Digital Access, Inc. (Lumentum Holdings Inc.)
• Inventors: Hartmann, Paul R., Cadieux, Kevin, Pope, Kevin, Engdahl, Thomas L.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): BLUM, RUSSELL
• Application Number:
  US08/451,676
• Time in Patent Office: 697 Days
• Field of Search: 370/13, 370/14, 370/17, 370/91, 370/94.2, 371/20.1, 379/1, 379/9, 379/10, 379/11, 379/14, 379/15, 379/16, 379/17, 379/22, 379/23, 379/24
• US Class Current: 370/241
• CPC Class Codes: H04J 3/0608 Detectors therefor, e.g. correlators, state machines
• CPC Class Codes: H04J 3/0623 Synchronous multiplexing systems, e.g. synchronous digital hierarchy/synchronous optical network (SDH/SONET), synchronisation with a pointer process
• CPC Class Codes: H04J 3/14 Monitoring arrangements for SDH/SONET rings H04J3/085
• CPC Class Codes: H04M 3/22 Arrangements for supervision, monitoring or testing
• CPC Class Codes: H04M 3/244 for multiplex systems

Abstract

A DS3 level access, monitor and test system for a telephone network. The system provides selective, and hitless, bit overwrite in any of the embedded DS1, DS0 and substrate channels in a DS3 signal. Multiple DS0 and subrate channels can be tested via the asynchronous time slot interchange in conjunction with the recombiner of the present invention. The present invention further includes a lookahead reframer for framing to the DS3 signal. The present invention also includes a facilities data link (FDL) handler for capturing the FDL channel data in every DS1 channel in a DS3 signal. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.

Claims

1. A maintenance system for a signal having a plurality of embedded communication channels, the system comprising:

a receiver for receiving the signal;

an access circuit for simultaneously accessing at least a portion of the channels, wherein each channel is asynchronous to the signal;

a circuit selectively overwriting one or more bits in at least one of the accessed channels at the signal rate, wherein the bit order of the signal is maintained; and

a performance monitor for continuously monitoring the signal and the accessed channels.

2. The system defined in claim 1, additionally comprising a test resource for testing the accessed channels.

3. The system defined in claim 1, wherein the channels are multiplexed.

4. The system defined in claim 1, wherein the maintenance system communicates with a network management center.

5. The system defined in claim 1, wherein the communication channels are received from a telecommunications network.

6. The system defined in claim 1, wherein the rate of one of the communication channels is greater than 10 Megabits per second.

7. The system defined in claim 1, wherein one of the communication channels is DS3.

8. The system defined in claim 1, wherein the signal is a DS3 signal.

9. The system defined in claim 1, wherein the signal is a SONET signal.

10. The system defined in claim 1, wherein the signal is digitally multiplexed as defined by CCITT.

11. The system defined in claim 1, wherein each of the embedded communication channels is a DS1 channel.

12. The system defined in claim 1, wherein each of the embedded communication channels comprises a plurality of subordinate embedded channels.

13. The system defined in claim 12, wherein each of the subordinate embedded channels is a DS0 channel.

14. The system defined in claim 12, wherein any at least one of the subordinate embedded channels is monitored.

15. A performance monitoring system for a signal having embedded channels, the system comprising:

a shared resource providing access to at least a portion of the embedded channels;

means for continuously monitoring the accessed channels in the signal, wherein each channel is asynchronous to the signal;

a circuit selectively overwriting one or more bits in at least one of the accessed channels at the signal rate, wherein the bit order of the signal is maintained; and

means for continuously monitoring the accessed channels simultaneously with the signal.

16. The system defined in claim 15, wherein the signal is a DS3 signal.

17. The system defined in claim 16, wherein the embedded channels are DS1 channels.

18. The system defined in claim 15, additionally comprising means for testing the embedded channels, wherein the testing and monitoring occur simultaneously.

19. The system defined in claim 15, wherein the channels are multiplexed.

20. The system defined in claim 15, wherein each of the embedded channels comprises a plurality of subordinate embedded channels.

21. The system defined in claim 20, wherein each of the subordinate embedded channels is a DS0 channel.

22. The system defined in claim 20, wherein any at least one of the subordinate embedded channels is monitored.

23. In a maintenance system for a signal having a plurality of embedded communication channels, a method of performance monitoring an accessed channel, the method comprising the steps of:

receiving the signal;

simultaneously accessing the channels, wherein each channel is asynchronous to the signal;

selectively overwriting one or more bits in at least one of the accessed channels at the signal rate, wherein the bit order of the signal is maintained; and

continuously monitoring the signal and the accessed channels.

24. The method defined in claim 23, additionally comprising the step of simultaneously testing the accessed channels.

25. The method defined in claim 23, wherein the channels are multiplexed.

26. The method defined in claim 23, wherein the communication channels are DS3.

27. The method defined in claim 23, wherein the communication channels are DS1.

28. The method defined in claim 23, wherein the signal is a DS3 signal.

29. The method defined in claim 23, wherein the signal is a SONET signal.

30. The method defined in claim 23, wherein each of the embedded communication channels comprises a plurality of subordinate embedded channels.

31. The method defined in claim 30, wherein each of the subordinate embedded channels is a DS0 channel.

32. The method defined in claim 30, additionally comprising the step of monitoring any at least one of the subordinate embedded channels.

36. The system defined in claim 30, wherein each of the embedded communication channels comprises a plurality of subordinate embedded channels.

37. The system defined in claim 36, wherein each of the subordinate embedded channels is a DS0 channel.

38. The system defined in claim 36, wherein any at least one of the subordinate embedded channels is monitored.

33. A performance monitoring and testing system for a signal having embedded channels, the system comprising:

a shared resource providing access to at least a portion of the embedded channels;

means for continuously monitoring the accessed channels in the signal, wherein each channel is asynchronous to the signal;

a circuit selectively overwriting one or more bits in at least one of the accessed channels at the signal rate, wherein the bit order of the signal is maintained; and

means for testing at least one accessed channel, wherein the testing and monitoring occur simultaneously.

34. The system defined in claim 33, wherein the signal is a DS3 signal.

35. The system defined in claim 33, wherein each of the embedded channels is a DS1 channel.

39. In a maintenance system for a signal having a plurality of embedded communication channels, a method of performance monitoring and testing an accessed channel, the method comprising the steps of:

receiving the signal;

simultaneously accessing the channels, wherein each channel is asynchronous to the signal;

continuously monitoring the signal and the accessed channels;

selectively overwriting one or more bits in at least one of the accessed channels at the signal rate, wherein the bit order of the signal is maintained; and

testing at least one of the accessed channels, wherein the testing step and monitoring step are performed simultaneously.

40. The method defined in claim 39, wherein the channels are multiplexed.

41. The method defined in claim 39, wherein the signal is a DS3 signal.

42. The method defined in claim 39, wherein each of the embedded communication channels is a DS1 channel.

43. The method defined in claim 39, wherein each of the embedded communication channels comprises a plurality of subordinate embedded channels.

44. The method defined in claim 43, wherein each of the subordinate embedded channels is a DS0 channel.

45. The method defined in claim 43, additionally comprising the step of monitoring any at least one of the subordinate embedded channels.