Method and circuit arrangement for transmitting binary data trains
First Claim
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1. A method for transmitting a binary data train of 0 data bits or 1 data bits, comprising the steps of:
- generating an encoded baseband signal by converting the binary data train into a plurality of pulses whose polarity changes from one pulse to a next pulse, such that for each 1 data bit a pulse is generated while for each 0 data bit the pulse is returned to zero, or, alternatively, for each 0 data bit a pulse is generated while for each 1 data bit the pulse is returned to zero;
shaping the pulses prior to transmission so as to minimize an occurrence of an inter-symbol interference and interfering harmonics; and
transmitting the shaded pulses over a communication channel to a receiving station;
the receiving station comprising the step of;
converting the transmitted shaped pulses into the original binary data train of 0 data bits or 1 data bits with the aid of a synchronized clock signal.
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Abstract
A method and apparatus for transmitting binary data trains of 0 and 1 data bits, or combinations of these data bits over a communications network. The data bits are converted into pulses whose polarity changes from pulse to pulse, so as to enable an optimal exploitation of the transmission channel with a low error rate. The pulses generated by an apparatus of the present invention have a signal shape that produces a minimum inter-symbol interference. Processing and evaluation of the transmitted pulses are performed by a processor, so that a minimal error rate is attainable even under unfavorable transmission conditions.
62 Citations
28 Claims
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1. A method for transmitting a binary data train of 0 data bits or 1 data bits, comprising the steps of:
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generating an encoded baseband signal by converting the binary data train into a plurality of pulses whose polarity changes from one pulse to a next pulse, such that for each 1 data bit a pulse is generated while for each 0 data bit the pulse is returned to zero, or, alternatively, for each 0 data bit a pulse is generated while for each 1 data bit the pulse is returned to zero; shaping the pulses prior to transmission so as to minimize an occurrence of an inter-symbol interference and interfering harmonics; and transmitting the shaded pulses over a communication channel to a receiving station; the receiving station comprising the step of; converting the transmitted shaped pulses into the original binary data train of 0 data bits or 1 data bits with the aid of a synchronized clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An apparatus in which a binary data train of 0 data bits or 1 data bits or combinations of 0 and 1 data bits is transferred over a communications network with further data equipment devices, comprising:
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a processor that converts the binary data train into a plurality of pulses whose polarity changes from one pulse to a next pulse, said processor comprising; a digital signal processor; a counter that is interfaced to said digital signal processor; a pulse width modulator that is interfaced with said counter; and a pulse width demodulator that receives a signal from said pulse width modulator; means for transmitting pulses representing one of 0 data bits, 1 data bits, and combinations of 0 and 1 data bits, to a receiving station over the communications network, said combinations of data bits being provided such that said pulses have different amplitudes and are transmitted for at least two of the bit combinations represented as 11, 10, 01 and 00; and means for converting the transmitted pulses at said receiving station into their original data bits or data bit combinations.
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10. An apparatus in which a binary data train of 0 and 1 data bits is transferred over a communications network with further data equipment devices, comprising:
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a data bus; a processor connected to said data bus; a counter that counts data received from said processor; a pulse width modulator that transmits data received from said counter; means for coupling said pulse width modulator to said communications network; and a controller that controls said processor and said counter. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A method for transmitting a binary data train of 0 data bits or 1 data bits, comprising the steps of:
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generating an encoded baseband-signal by converting the binary data train into a plurality of pulses whose polarity changes from one pulse to a next pulse; rearranging the 0 data bits and the 1 data bits in such a way that a data train of dual-bit-units containing 11 or 00, dual-bit-units containing 10 or 01 and single-bit-units containing 0 or 1 are formed; selecting single-bit-units in accordance with one of the following conditions; (a) single-bit-units containing 0 are selected for rearrangement when dual-bit-units containing 11 are selected, and (b) single-bit-units containing 1 are selected for rearrangement when dual-bit-units containing 00 are selected; assigning pulses of different amplitudes to the dual-bit-units of a selected set, where for each dual-bit-unit a corresponding pulse is generated while for each single-bit-unit the pulse is returned to zero; shaping the pulses prior to transmission so as to minimize the occurrence of an inter-symbol interference and interfering harmonics; and transmitting the shaped pulses over a communication channel to a receiving station; the receiving station comprising the step of; converting the transmitted shaped pulses into the original binary data train of 0 data bits or 1 data bits with the aid of a synchronized clock signal. - View Dependent Claims (25, 26, 27, 28)
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Specification