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Memory access control system which prohibits a memory access request to allow a central control unit to perform software operations

  • US 5,623,622 A
  • Filed: 09/30/1992
  • Issued: 04/22/1997
  • Est. Priority Date: 10/08/1991
  • Status: Expired due to Fees
First Claim
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1. A memory access control system which performs a DMA transfer, the memory access control system being responsive to a specific software operation and comprising:

  • a central control unit which includes a flag and runs the specific software operation, the central control unit setting the flag after the running of the specific software operation is completed;

    a main memory which is coupled to the central control unit;

    a file memory control unit which comprisesfirst and second buffer memories, the DMA transfer including a first phase and a second phase, the first phase being a first transfer between the main memory and the first buffer memory and then a successive, second transfer between the main memory and the second buffer memory, the second phase being a transfer between a respective buffer memory of the first and second buffer memories and an external memory, the second phase being performed for a respective buffer memory after a transfer between the main memory and the respective buffer memory in the first phase,an external memory controller for controlling the external memory,a first DMA controller for requesting the first phase of a DMA transfer and for controlling the second phase, the first DMA controller controlling the transfer of the second phase from a respective buffer memory when a transfer of the first phase from the main memory to the respective buffer memory ends, and prohibiting a request for the first phase when the first transfer ends during a transfer of the second phase from the second buffer memory, anda DMA request controller which is coupled to the first DMA controller and controls the request for the first phase by the first DMA controller, the DMA request controller prohibiting a request for the first phase by the first DMA controller when the second transfer of the first phase ends and cancelling the prohibition of a request for the first phase when the flag of the central control unit is set; and

    an external bus control unit, coupled between the main memory and the first and second buffer memories, which, in response to a request for the first phase, halts the operation of the central control unit and performs the first and second transfers of the first phase, and stops halting the operation of the central control unit when a request for the first phase is prohibited.

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