Memory access control system which prohibits a memory access request to allow a central control unit to perform software operations

• US 5,623,622 A
• Filed: 09/30/1992
• Issued: 04/22/1997
• Est. Priority Date: 10/08/1991
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Igi, Yoso, Yuki, Keiko, Tahira, Fumiaki
• Primary Examiner(s): Elmore, Reba I.
• Application Number:
  US07/953,965
• Time in Patent Office: 1,665 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 395/400 MS File, 395/425 MS File
• US Class Current: 711/100
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A memory access control system which performs a DMA transfer and allows a central control unit to perform a specific, required software operation. A central control unit sets a flag after running the specific software operation. The DMA transfer includes a first phase and a second phase, the first phase being a first transfer between a main memory and a first buffer memory and then a successive, second transfer between the main memory and a second buffer memory. The second phase is a transfer between a respective buffer memory and an external memory. A first DMA controller requests the first phase and controls the transfer of the second phase from a respective buffer memory when a transfer of the first phase from the main memory to the respective buffer memory ends, and prohibits a request for the first phase when the first transfer ends during a transfer of the second phase from the second buffer memory. A DMA request controller controls the request for the first phase and prohibits a request when the second transfer of the first phase ends and cancels the prohibition of a request when the flag of the central control unit is set. In response to a request for the first phase, an external bus control unit halts the operation of the central control unit and performs the first and second transfers of the first phase.

Claims

1. A memory access control system which performs a DMA transfer, the memory access control system being responsive to a specific software operation and comprising:

a central control unit which includes a flag and runs the specific software operation, the central control unit setting the flag after the running of the specific software operation is completed;

a main memory which is coupled to the central control unit;

a file memory control unit which comprises

first and second buffer memories, the DMA transfer including a first phase and a second phase, the first phase being a first transfer between the main memory and the first buffer memory and then a successive, second transfer between the main memory and the second buffer memory, the second phase being a transfer between a respective buffer memory of the first and second buffer memories and an external memory, the second phase being performed for a respective buffer memory after a transfer between the main memory and the respective buffer memory in the first phase,

an external memory controller for controlling the external memory,

a first DMA controller for requesting the first phase of a DMA transfer and for controlling the second phase, the first DMA controller controlling the transfer of the second phase from a respective buffer memory when a transfer of the first phase from the main memory to the respective buffer memory ends, and prohibiting a request for the first phase when the first transfer ends during a transfer of the second phase from the second buffer memory, and

a DMA request controller which is coupled to the first DMA controller and controls the request for the first phase by the first DMA controller, the DMA request controller prohibiting a request for the first phase by the first DMA controller when the second transfer of the first phase ends and cancelling the prohibition of a request for the first phase when the flag of the central control unit is set; and

an external bus control unit, coupled between the main memory and the first and second buffer memories, which, in response to a request for the first phase, halts the operation of the central control unit and performs the first and second transfers of the first phase, and stops halting the operation of the central control unit when a request for the first phase is prohibited.

2. The memory access control system as claimed in claim 1, further comprising:

a first bus which couples the central control unit and the main memory, wherein said file memory control unit comprises a second bus which is coupled to the first and second buffer memories, said external bus control unit being coupled to the first and second buses.

3. The memory access control system as claimed in claim 2, wherein the file memory control unit further comprises a third bus which couples the first DMA controller, the external memory controller and the first and second buffer memories.

4. The memory access control system as claimed in claim 1, wherein said external bus control unit includes a second DMA controller, coupled to the DMA request controller, for controlling transfers between the main memory and the file memory control unit.

5. The memory access control system as claimed in claim 1, wherein the external memory comprises at least one of a floppy disk unit and a hard disk unit.

6. The memory access control system as claimed in claim 5, wherein the external memory controller comprises a floppy disk controller for controlling the floppy disk unit, and a protocol controller for controlling the hard disk unit.

7. The memory access control system as claimed in claim 1, wherein the central control unit further comprises:

a timer which counts a predetermined time from when the DMA request controller cancels the prohibition of a request for the first phase, wherein the DMA request controller cancels the prohibition of a request for the first phase when the flag of the central control unit is not set within the predetermined time counted by the timer.

8. The memory access control system as claimed in claim 7, further comprising:

a communication line which bypasses the external bus control unit and connects the central control unit to the file memory control unit, wherein, when the flag of the central control unit is not set within the predetermined time, the central control unit transmits a signal to the file memory control unit via the communication line.

9. The memory access control system as claimed in claim 1, wherein a data transfer speed between the main memory and the first and second buffer memories is approximately the same as a data transfer speed between the first and second memories and the external memory.

10. The memory access control system as claimed in claim 1, wherein a data transfer speed between the main memory and the first and second buffer memories is less that or equal to a data transfer speed between the first and second memories and the external memory.