Interactive memory organization system and method therefor

• US 5,623,664 A
• Filed: 07/25/1994
• Issued: 04/22/1997
• Est. Priority Date: 07/25/1994
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Claus, Arthur H., France, Robert B., Calvert, Brian E.
• Primary Examiner(s): Kriess, Kevin A.
• Application Number:
  US08/279,605
• Time in Patent Office: 1,002 Days
• Field of Search: 395/700, 395/650, 395/155, 395/156, 395/157, 395/159, 395/161
• US Class Current: 713/1
• CPC Class Codes: G06F 11/2289 by configuration test
• CPC Class Codes: G06F 9/5016 the resource being the memory

Abstract

A method, referred to as the interactive memory mapper or IMM (322), allows a user to program a memory (9) of a data processor (14) using a computer terminal (12) as a visual interface. The IMM allows a user to view and modify a pictorial representation of a data processor'"'"'s memory space. When the IMM is utilized to allow the plurality of memory blocks to be viewed on the computer terminal, each block has visible attributes corresponding to the memory located at a memory address. Each of the plurality of memory blocks may be selected using a pointing device or keyboard and the blocks'"'"' attributes may be modified via an auxiliary controls subroutine (90) of the IMM program. The selected blocks may be created, moved, and resized to either add or subtract additional memory space, but is constrained to legal configurations determined by the specification of the data processor.

Claims

1. A method for programming a data processing memory system, comprising the steps of:

storing a software program in a memory unit of the data processing memory system;

storing a plurality of parameters for modeling a data processor, the plurality of parameters indicating a memory organization of the data processor;

receiving a first user input for initiating the software program at an interface circuit, the interface circuit being coupled to the memory unit;

processing the first user input in a central processing unit to generate and communicate a plurality of data signals, a plurality of address signals, and a plurality of control signals to the memory circuit, the central processing unit being coupled to the interface circuit for communicating the first user input and being coupled to the memory circuit for communicating the plurality of data signals, the plurality of address signals, and the plurality of control signals;

accessing the software program in the memory unit using the plurality of data signals, the plurality of address signals, and the plurality of control signals, the software program providing a first video interface on a terminal of the data processing memory system, the first video interface illustrating a first memory organization of the data processor;

receiving a second user input for modifying a first portion of the first memory organization of the data processor; and

accessing the software program in the memory circuit to determine if the second user input modifying the first portion of the first memory organization results in a first allowable memory configuration of the data processor.

2. The method of claim 1 further comprising the step of:

modifying the first video interface to illustrate a second memory organization of the data processor when the software program in the memory unit determines the second user input modifying the first portion or the first memory organization results in the first allowable memory configuration of the data processor, the first video interface remaining unchanged to illustrate the first memory organization of the data processor when the software program in the memory unit determines the second user input modifying the first portion of the first memory organization is not the first allowable memory configuration of the data processor.

3. The method of claim 1 wherein the data processor is the data processing memory system.

4. The method of claim 1 wherein one of the plurality of parameters for modeling the data processor indicates a base address of the first memory organization.

5. The method of claim 4 wherein a first chip select signal is asserted when a first one of the plurality of address signals is included in an address range defined by the base address and a size value.

6. The method of claim 1 wherein one of the plurality of parameters for modeling the data processor indicates a size of the first memory organization.

7. The method of claim 1 wherein one of the plurality of parameters for modeling the data processor indicates a bit width of the first memory organization.

8. The method of claim 1 wherein one of the plurality of parameters for modeling the data processor indicates an access right of the first memory organization.

9. The method of claim 1 wherein the first user input and the second user input are provided by one of a keyboard and a pointing device.

10. The method of claim 1 wherein the plurality of parameters are analyzed to determine if the second user input modifying the first portion of the first memory organization results in the first allowable memory configuration of the data processor.

11. The method of claim 1 further comprising the steps of:

receiving a third user input for modifying a second portion of the first memory organization of the data processor; and

accessing the software program in the memory unit to determine if the third user input modifying the second portion of the first memory organization results in a second allowable memory configuration of the data processor.

12. The method of claim 11 further comprising the steps of:

modifying the first video interface to provide a second video interface which illustrates a second memory organization of the data processor when the software program in the memory unit determines the second user input modifying the first portion of the first memory organization results in the first allowable memory configuration of the data processor and the third user input modifying the second portion of the first memory organization results in the second allowable memory configuration of the data processor; and

enabling the first video interface to remain unchanged and to illustrate the first memory organization of the data processor when the software program in the memory unit determines one of the second user input modifying the first portion of the first memory organization is not the first allowable memory configuration of the data processor and the third user input modifying the second portion of the first memory organization is not the second allowable memory configuration of the data processor.

13. The method of claim 12 wherein the second portion of the first memory organization is placed in front of the first portion of the first memory organization when the third user input is received.

14. The method of claim 12 wherein the first portion of the first memory organization is placed in front of the second portion of the first memory organization when the second user input is received.

15. The method of claim 1 further comprising the step of:

placing a pile marker on the first video interface to indicate the first portion of the first memory organization overlaps a second portion of the first memory organization.

16. A method for programming a data processing memory system, comprising the steps of:

storing a software program in a memory circuit of the data processing memory system;

storing a plurality of parameters for modeling a data processor, the plurality of parameters indicating a memory organization of the data processor;

receiving a first user input for initiating the software program at an interface circuit, the interface circuit being coupled to the memory circuit;

processing the first user input in a central processing unit to generate and communicate a plurality of data signals, a plurality of address signals, and a plurality of control signals to the memory circuit, the central processing unit being coupled to the interface circuit for communicating the first user input and being coupled to the memory circuit for communicating the plurality of data signals, the plurality of address signals, and the plurality of control signals;

accessing the software program in the memory unit using each of the plurality of data signals, the plurality of address signals, and the plurality of control signals, the software program providing a first video interface on a terminal of the data processing memory system, the first video interface illustrating a first memory organization and a first group of attributes of the data processor;

receiving a second user input to begin modifying the first memory organization of the data processor;

providing a second video interface of the terminal of the data processing memory system, the second video interface illustrating a second memory organization of the data processor;

receiving a third user input to end modifying the first memory organization of the data processor; and

providing a third video interface of the terminal of the data processing memory system, the third video interface illustrating a third memory organization of the data processor and a second group of attributes when the third memory organization is a first allowable memory configuration.

17. The method of claim 16 wherein the third video interface illustrates the first memory organization of the data processor and the first group of attributes when the third memory organization is an unallowable memory configuration.

18. The method of claim 16 wherein a first one of the plurality of parameters for modeling the data processor indicates a base address of the first memory organization, a second one of the plurality of parameters for modeling the data processor indicates a size of the first memory organization, a third one of the plurality of parameters for modeling the data processor indicates a bit width of the first memory organization, and a fourth one of the plurality of parameters for modeling the data processor indicates an access right of the first memory organization.

19. The method of claim 18 wherein a first chip select signal is asserted when a first one of the plurality of address signals is included in an address range defined by the base address and the size.

20. The method of claim 16 wherein the first user input, the second user input, and the third user input are provided by one of a keyboard and a pointing device.

21. The method of claim 16 further comprising the steps of:

receiving a fourth user input for modifying a second portion of the first memory organization of the data processor; and

accessing the software program in the memory unit to determine if the fourth user input modifying the second portion of the first memory organization results in a second allowable memory configuration of the data processor.

22. The method of claim 21 further comprising the steps of:

modifying the first video interface to provide the third video interface which illustrates the third memory organization of the data processor when the software program in the memory unit determines the third user input modifying the first portion of the first memory organization results in the first allowable memory configuration of the data processor and the fourth user input modifying the second portion of the first memory organization results in the second allowable memory configuration of the data processor; and

enabling the first video interface to remain unchanged and to illustrate the first memory organization of the data processor when the software program in the memory unit determines one of the third user input modifying the first portion of the first memory organization is not the first allowable memory configuration of the data processor and the fourth user input modifying the second portion of the first memory organization is not the second allowable memory configuration of the data processor.

23. The method of claim 22 further comprising the step of:

placing a pile marker on the first video interface to indicate the first portion of the first memory organization overlaps the second portion of the first memory organization.

24. The method of claim 23 wherein the second portion of the first memory organization is placed in front of the first portion of the first memory organization on the third video interface when the fourth user input is received.

25. The method of claim 23 wherein the first portion of the first memory organization is placed in front of the second portion of the first memory organization on the fourth video interface when a sixth user input is received.