Video game enhancer with intergral modem and smart card interface

• US 5,624,316 A
• Filed: 06/06/1994
• Issued: 04/29/1997
• Est. Priority Date: 06/06/1994
• Status: Expired due to Fees

• Current Assignee: HearMe (Palktalk.com)
• Original Assignee: Catapult Entertainment, Inc. (Palktalk.com)
• Inventors: Perlman, Stephen G., Roskowski, Steven G.
• Primary Examiner(s): Harrison, Jessica
• Assistant Examiner(s): ONEILL, MICHAEL W
• Application Number:
  US08/254,154
• Time in Patent Office: 1,058 Days
• Field of Search: 273/433, 273/436, 273/439, 273/DIG. 28, 273/148 B, 364/410, 364/411, 463/45, 463/41
• US Class Current: 463/45
• CPC Class Codes: A63F 13/48 Starting a game, e.g. activating a game device or waiting for other players to join a multiplayer session
• CPC Class Codes: A63F 13/95 Storage media specially adapted for storing game information, e.g. video game cartridges
• CPC Class Codes: A63F 13/98 Accessories, i.e. detachable arrangements optional for the use of the video game device, e.g. grip supports of game controllers
• CPC Class Codes: A63F 2300/206 Game information storage, e.g. cartridges, CD ROM's, DVD's, smart cards
• CPC Class Codes: A63F 2300/636 involving process of starting or resuming a game

Abstract

A video game enhancement system for modifying and enhancing the operation of a video game is disclosed. The system includes: 1) a processor interface for coupling the video game enhancement system with a processor; 2) a memory interface for coupling the video game enhancement system with a first memory having executable game logic residing therein; 3) a second memory having executable enhancement logic residing therein; and 4) control logic including: a) logic for detecting an access to a patch address by the processor; b) logic for directing the processor to access an exception region in the second memory upon detection of the access to the patch address, the access to the exception region causing activation of an exception mode; and c) redirection logic for redirecting memory accesses by the processor from the first memory to the second memory for a plurality of memory accesses upon activation of the exception mode, the processor thereby executing a portion of the executable enhancement logic. The the control logic of the video game enhancement system also includes: 5) logic for detecting an access to a transition address by the processor; 6) logic for directing the processor to terminate the exception mode upon detection of the access to the transition address; and 7) the redirection logic further includes logic for redirecting memory accesses by the processor from the second memory to the first memory upon termination of the exception mode, the processor thereby continuing execution of the executable game logic.

Claims

1. A video game enhancement apparatus for modifying and enhancing the operation of a video game, said apparatus coupled to a processor and a first memory, said first memory having a means for executing said video game, said apparatus comprising:

a processor interface for coupling said apparatus with said processor;

a memory interface for coupling said apparatus with said first memory;

a second memory having a means for enhancing the operation of said video game in said first memory, said means for enhancing the operation of said video game including;

a means for generating a first trigger signal upon a predetermined processor access to said first memory;

a means for redirecting said predetermined processor access from said first memory to a patch address in said second memory, said patch address having a pointer to a patch table having a plurality of instructions, each of said plurality of instructions corresponding to a plurality of data;

a means for activating an exception mode; and

a means for executing one of said plurality of instructions in said patch table in said second memory.

2. The video game enhancement apparatus as claimed in claim 1 wherein said means for enhancing the operation of said video game further includes:

a means for generating a second trigger signal upon a predetermined processor access to said second memory; and

a means for redirecting said predetermined processor access from said second memory to said first memory, thereby continuing operation of said video game in said first memory.

3. The video game enhancement apparatus as claimed in claim 1 wherein said means for redirecting said predetermined processor access from said first memory to said second memory includes a means for accessing said first memory that does not overlap access to said second memory.

4. The video game enhancement apparatus as claimed in claim 1 wherein said means for redirecting said predetermined processor access from said first memory to said second memory includes a means for accessing said first memory that overlaps access to said second memory.

5. The video game enhancement apparatus as claimed in claim 1 wherein said means for redirecting said predetermined processor access from said first memory to said patch address in said second memory further includes a means for substituting a new instruction from said plurality of instructions in said patch table for an original instruction stored in said first memory.

6. The video game enhancement apparatus as claimed in claim 5 wherein said new instruction is a trap instruction.

7. The video game enhancement apparatus as claimed in claim 1 wherein said means for redirecting said predetermined processor access from said first memory to said patch address in said second memory further includes a means for substituting new data stored in said second memory for original data stored in said first memory.

8. The video game enhancement apparatus as claimed in claim 1 wherein the contents of said patch table are modifiable by said processor.

9. The video game enhancement apparatus as claimed in claim 1 wherein said means for redirecting said predetermined processor access from said first memory to said patch table in said second memory further includes a means for disabling said means for redirecting upon said processor access to a location outside of a predetermined address range while said exception mode is active.

10. The video game enhancement apparatus as claimed in claim 9 wherein said processor access to a location outside of a predetermined address range while said exception mode is active is a DMA access.

11. The video game enhancement apparatus as claimed in claim 1 wherein said means for redirecting said predetermined processor access from said first memory to said patch table in said second memory further includes a means for disabling said means for redirecting upon said processor access to a location within a predetermined address range while said exception mode is active.

12. The video game enhancement apparatus as claimed in claim 1 further including a counter for counting a number of times that said exception mode is activated, said counter also for counting a number of times that said exception mode is terminated, said means for redirecting said predetermined processor access from said first memory to said patch address in said second memory further including a means for incrementing said counter upon activation of said exception mode and terminating said exception mode only if said counter is equal to zero.

13. The video game enhancement apparatus as claimed in claim 1 further including an insertable removable card interface for coupling said apparatus to an insertable removable card.

14. The video game enhancement apparatus as claimed in claim 1 further including a modem connection for coupling said apparatus to a modem.

15. A network video game enhancement system for modifying and enhancing the operation of a video game, said system comprising:

a network;

a processor;

a modem coupled to said processor, said modem for connecting said processor to said network;

a first memory coupled to said processor, said first memory having a means for executing said video game; and

a second memory coupled to said processor, said second memory having a means for enhancing the operation of said video game, said means for enhancing the operation of said video game including

a means for generating a first trigger signal upon a predetermined processor access to said first memory;

a means for redirecting said predetermined processor access from said first memory to a patch address in said second memory, said patch address having a pointer to a patch table having a plurality of instructions, each of said plurality of instructions corresponding to a plurality of data;

a means for activating an exception mode;

a means for executing one of said plurality of instructions in said patch table in said second memory;

a means for generating a second trigger signal upon a predetermined processor access to said second memory; and

a means for redirecting said predetermined processor access from said second memory to said first memory upon activation of said second trigger signal, thereby continuing operation of said video game in said first memory.

16. The network video game enhancement system as claimed in claim 15 wherein said network is a telephone network.

17. The network video game enhancement system as claimed in claim 15 wherein said network is a cable television network.

18. The network video game enhancement system as claimed in claim 15 further including:

a means for connecting said video game system to a server on said network;

a means for downloading information from said server to said second memory; and

a means for altering functionality of said video game based on said information received from said server.