Vertical field effect transistor and method

• US 5,624,860 A
• Filed: 06/07/1995
• Issued: 04/29/1997
• Est. Priority Date: 04/30/1993
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Yuan, Han-Tzong, Plumton, Donald L.
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): DUTTON, BRIAN KEITH
• Application Number:
  US08/485,539
• Time in Patent Office: 692 Days
• Field of Search: 257/192, 257/194, 257/136, 257/263, 257/264, 257/265, 257/266, 437/24, 437/133, 437/911, 437/40 CS, 437/41 GS, 437/41 CS, 437/40 JF, 437/41 JF
• US Class Current: 438/193
• CPC Class Codes: H01L 21/02395 Arsenides
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02463 Arsenides
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/66318 Heterojunction transistors
• CPC Class Codes: H01L 29/66924 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/7371 Vertical transistors
• CPC Class Codes: H01L 29/7722 using static field induced regions, e.g. SIT, PBT

Abstract

A vertical field effect transistor (700) and fabrication method with buried gates (704) having gate sidewall crystal orientation the same as the substrate surface and a low index substrate crystal orientation without tilt to a higher index direction. The gate (704) may have modulated doping along the channel (706), and the drain (708) may have a lighter doping level than the channel which may be accomplished by an epitaxial overgrowth of the gates (704) to form the channels (706).

Claims

1. A method of fabrication of a vertical field effect transistor, comprising the steps of:

(a) providing a semiconductor drain layer having a first doping type;

(b) forming a first gate layer on said drain layer, said first gate layer having a doping type opposite said first doping type;

(c) forming a second gate layer on said first gate layer, said second gate layer having said doping type opposite said first doping type and a doping level different from the doping level of said first gate layer;

(d) removing portions of said first and second gate layers to define gate fingers; and

(e) forming channel regions between said gate fingers and forming a source region over said gate regions and channel regions.

2. The method of claim 1, wherein:

(a) said step of removing is by anisotropic etching; and

(b) said step of forming channel regions and a source region is by epitaxial growth.

3. The method of claim 2, wherein:

(a) said drain layer, said first gate layer, said second gate layer, said channel regions, and said source region are made of doped gallium arsenide.

4. The method of claim 3, wherein:

(a) said first and second gate layers are doped with carbon; and

(b) said channel regions and source region are doped with silicon.