Semiconductor processing method of forming complementary N-type doped and P-type doped active regions within a semiconductor substrate

• US 5,624,863 A
• Filed: 07/17/1995
• Issued: 04/29/1997
• Est. Priority Date: 07/17/1995
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Helm, Mark, Dennison, Charles
• Primary Examiner(s): TSAI, H JEY
• Application Number:
  US08/503,199
• Time in Patent Office: 652 Days
• Field of Search: 437/52, 437/47, 437/60, 437/162, 437/191, 437/193
• US Class Current: 438/210
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass
• CPC Class Codes: Y10S 148/123 Polycrystalline diffuse anneal

Abstract

A semiconductor processing method of forming complementary first conductivity type doped and second conductivity type doped active regions within a semiconductor substrate includes, a) providing a semiconductor substrate; b) masking a desired first conductivity type region of the substrate while conducting second conductivity type doping into a desired second conductivity type active region of the substrate; c) providing an insulating layer over the substrate over the desired first conductivity type region and the second conductivity type doped region; d) patterning the insulating layer to provide a void therethrough to the desired first conductivity type region; e) filling the void with a first conductivity type doped polysilicon plug, the plug having a first conductivity type dopant impurity concentration of at least 1×10²⁰ ions/cm³, the desired first conductivity type region having a first conductivity type dopant concentration prior to the filling step which is in the range of from 0 ions/cm³ to 1×10¹⁹ ions/cm³ ; and f) annealing the substrate for a period of time effective to out-diffuse first conductivity type dopant impurity from the first conductivity type doped polysilicon plug into the substrate to form the desired first conductivity type active region having a first conductivity type dopant impurity concentration of at least 1×10²⁰ ions/cm³ in the substrate. Methods of forming CMOS FET transistors, and SRAM and DRAM CMOS circuitry are also disclosed.

Claims

1. A semiconductor processing method of forming complementary n-type doped and p-type doped active regions within a semiconductor substrate, the method comprising the following steps:

providing a semiconductor substrate;

masking a desired n-type region of the substrate while conducting p-type conductivity doping into a desired p-type active region of the substrate;

providing an insulating layer over the substrate over the desired n-type region and the p-type doped region;

patterning the insulating layer to provide a void therethrough to the desired n-type region;

filling the void with an n-type conductively doped polysilicon plug, the plug having an n-type dopant impurity concentration of at least 1×

10²⁰ ions/cm³, the desired n-type region having an n-type dopant concentration prior to the filling step which is in the range of from 0 ions/cm³ to 1×

10¹⁹ ions/cm³ ; and

annealing the substrate for a period of time effective to out-diffuse n-type dopant impurity from the n-type conductively doped polysilicon plug into the substrate to form the desired n-type active region having an n-type dopant impurity concentration of at least 1×

10²⁰ ions/cm³ in the substrate.

2. The semiconductor processing method of claim 1 wherein the polysilicon plug is provided with n-type dopant impurity of less than or equal 5×

10²⁰ ions/cm³.

3. The semiconductor processing method of claim 1 further comprising providing a blanket n-type dopant implant to a substrate concentration of less than 1×

10¹⁹ ions/cm³ into the desired n-type region and the desired p-type region prior to the masking step.

4. The semiconductor processing method of claim 1 further comprising providing a blanket n-type dopant implant to a substrate concentration of from 5×

10¹⁷ ions/cm³ to 1×

10¹⁹ ions/cm³ into the desired n-type region and the desired p-type region prior to the masking step.

5. The semiconductor processing method of claim 1 further comprising:

providing a first blanket n-type dopant implant to a substrate concentration of less than 1×

10¹⁹ ions/cm³ into the desired n-type region and the desired p-type region prior to the masking step; and

providing a second blanket n-type dopant implant to a substrate concentration of from 1×

10¹⁹ ions/cm³ to 5×

10²⁰ ions/cm³ into the desired n-type region and p-type region after the first blanket implant and prior to the masking step.

6. The semiconductor processing method of claim 1 wherein the void comprises a substantially circular cross-sectioned contact opening.

7. The semiconductor processing method of claim 1 wherein the void comprises an elongated trough.

8. A semiconductor processing method of forming CMOS dynamic random access memory within a semiconductor substrate, the memory comprising an array area and an area peripheral to the array, the peripheral area comprising complementary n-type field effect transistors and p-type field effect transistors, the method comprising the following steps:

providing a semiconductor substrate having a defined memory array area and a defined peripheral area;

providing first and second field effect transistor gates in the peripheral substrate area, the first gate to be utilized for formation of an n-type field effect transistor, the second gate to be utilized for formation of a p-type field effect transistor, the first gate defining opposing peripheral substrate regions for formation of desired opposing n-type substrate active regions, the second gate defining opposing peripheral substrate regions for formation of desired opposing p-type substrate active regions;

masking the first gate and the desired n-type regions of the peripheral substrate area while conducting p-type conductivity doping into the desired p-type regions of the peripheral substrate area;

providing an insulating layer over the peripheral substrate area over the desired n-type regions and the p-type doped regions;

patterning the insulating layer to provide a void therethrough to each desired n-type region;

filling the respective voids with an n-type conductively doped polysilicon plug, the plugs having an n-type dopant impurity concentration of at least 1×

10²⁰ ions/cm³ the desired n-type regions having an n-type dopant concentration prior to the filling step which is in the range of from 0 ions/cm³ to 1×

10¹⁹ ions/cm³ ;

annealing the substrate for a period of time effective to out-diffuse n-type dopant impurity from the n-type conductively doped polysilicon plugs into the substrate to form the desired n-type active regions having an n-type dopant impurity concentration of at least 1×

10²⁰ ions/cm³ in the substrate; and

providing a series of dynamic random access memory cells within the array, the memory cells comprising a series of n-type field effect transistors and associated capacitors.

9. The semiconductor processing method of claim 8 wherein the polysilicon plug are provided with n-type dopant impurity of less than or equal 5×

10²⁰ ions/cm³.

10. The semiconductor processing method of claim 8 further comprising providing a blanket n-type dopant implant to a substrate concentration of less than 1×

10¹⁹ ions/cm³ into the desired n-type regions and the desired p-type regions prior to the masking step.

11. The semiconductor processing method of claim 8 further comprising providing a blanket n-type dopant implant to a substrate concentration of from 5×

10¹⁷ ions/cm³ to 1×

10¹⁹ ions/cm³ into the desired n-type regions and the desired p-type regions prior to the masking step.

12. The semiconductor processing method of claim 8 further comprising:

providing a first blanket n-type dopant LDD implant to a substrate concentration of less than 1×

10¹⁹ ions/cm³ into the desired n-type regions and the desired p-type regions prior to the masking step;

after the first blanket implant, forming insulative spacers about sidewall edges of the first gate; and

after the first blanket implant and after the spacer formation and prior to the masking step, providing a second blanket n-type dopant implant to a substrate concentration of from 1×

10¹⁹ ions/cm³ to 1×

10²⁰ ions/cm³ into the desired n-type regions and p-type regions.

13. The semiconductor processing method of claim 8 wherein the voids comprise a substantially circular cross-sectioned contact opening.

14. The semiconductor processing method of claim 8 wherein the voids comprise an elongated trough.

15. A semiconductor processing method of forming CMOS static random access memory within a semiconductor substrate, the method comprising the following steps:

providing a semiconductor substrate;

providing first, second, third and fourth field effect transistor gates on the substrate, the first and second gates to be utilized for formation of cross-coupled SRAM n-type field effect driver transistors, the third and fourth gates to be utilized for formation of SRAM p-type field effect load transistors, the first and second gates defining respective opposing substrate regions for formation of desired opposing n-type substrate active regions, the third and fourth gates defining respective opposing substrate regions for formation of desired opposing p-type substrate active regions;

masking the first gate, the second gate and the desired n-type regions while conducting p-type conductivity doping into the desired p-type regions of the substrate;

providing an insulating layer over the substrate over the desired n-type regions and the p-type doped regions;

patterning the insulating layer to provide a void therethrough to each desired n-type region;

filling the respective voids with an n-type conductively doped polysilicon plug, the plugs having an n-type dopant impurity concentration of at least 1×

10²⁰ ions/cm³ the desired n-type regions having an n-type dopant concentration prior to the filling step which is in the range of from 0 ions/cm³ to 1×

10¹⁹ ions/cm³ ;

annealing the substrate for a period of time effective to out-diffuse n-type dopant impurity from the n-type conductively doped polysilicon plugs into the substrate to form the desired n-type active regions having an n-type dopant impurity concentration of at least 1×

10²⁰ ions/cm³ in the substrate;

electrically interconnecting one of the conductive plugs of the first driver transistor to one of the conductive plugs of the second driver transistor;

electrically interconnecting the other conductive plug of the first driver transistor with the second gate and with one of the p-type regions of one of the load transistors; and

electrically interconnecting the other conductive plug of the second driver transistor with the first gate and with one of the p-type regions of the other load transistor.

16. The semiconductor processing method of claim 15 wherein the polysilicon plugs are provided with n-type dopant impurity of less than or equal 5×

10²⁰ ions/cm³.

17. The semiconductor processing method of claim 15 further comprising providing a blanket n-type dopant implant to a substrate concentration of less than 1×

10¹⁹ ions/cm³ into the desired n-type regions and the desired p-type regions prior to the masking step.

18. The semiconductor processing method of claim 15 further comprising providing a blanket n-type dopant implant to a substrate concentration of from 5×

10¹⁷ ions/cm³ to 1×

10¹⁹ ions/cm³ into the desired n-type regions and the desired p-type regions prior to the masking step.

19. The semiconductor processing method of claim 15 further comprising:

providing a first blanket n-type dopant LDD implant to a substrate concentration of less than 1×

10¹⁹ ions/cm³ into the desired n-type regions and the desired p-type regions prior to the masking step;

after the first blanket implant, forming insulative spacers about sidewall edges of the first and second gates; and

after the first blanket implant and after the spacer formation and prior to the masking step, providing a second blanket n-type dopant implant to a substrate concentration of from 1×

10¹⁹ ions/cm³ to 1×

10²⁰ ions/cm³ into the desired n-type regions and p-type regions.

20. A semiconductor processing method of forming complementary first conductivity type doped and second conductivity type doped active regions within a semiconductor substrate, the method comprising the following steps:

providing a semiconductor substrate;

masking a desired first conductivity type region of the substrate while conducting second conductivity type doping into a desired second conductivity type active region of the substrate;

providing an insulating layer over the substrate over the desired first conductivity type region and the second conductivity type doped region;

patterning the insulating layer to provide a void therethrough to the desired first conductivity type region;

filling the void with a first conductivity type doped polysilicon plug, the plug having a first conductivity type dopant impurity concentration of at least 1×

10²⁰ ions/cm³ the desired first conductivity type region having a first conductivity type dopant concentration prior to the filling step which is in the range of from 0 ions/cm³ to 1×

10¹⁹ ions/cm³ ; and

annealing the substrate for a period of time effective to out-diffuse first conductivity type dopant impurity from the first conductivity type doped polysilicon plug into the substrate to form the desired first conductivity type active region having a first conductivity type dopant impurity concentration of at least 1×

10²⁰ ions/cm³ in the substrate.

21. The semiconductor processing method of claim 20 wherein the polysilicon plug is provided with first conductivity type dopant impurity of less than or equal 5×

10²⁰ ions/cm³.

22. The semiconductor processing method of claim 20 further comprising providing a blanket first conductivity type dopant implant to a substrate concentration of less than 1×

10¹⁹ ions/cm³ into the desired first conductivity type region and the desired second conductivity type region prior to the masking step.

23. The semiconductor processing method of claim 20 further comprising providing a blanket first conductivity type dopant implant to a substrate concentration of from 5×

10¹⁷ ions/cm³ to 1×

10¹⁹ ions/cm³ into the desired first conductivity type region and the desired second conductivity type region prior to the masking step.

24. The semiconductor processing method of claim 20 further comprising:

providing a first blanket first conductivity type dopant implant to a substrate concentration of less than 1×

10¹⁹ ions/cm³ into the desired first conductivity type region and the desired second conductivity type region prior to the masking step; and

providing a second blanket first conductivity type dopant implant to a substrate concentration of from 1×

10¹⁹ ions/cm³ to 5×

10²⁰ ions/cm³ into the desired first conductivity type region and second conductivity type region after the first blanket implant and prior to the masking step.

25. The semiconductor processing method of claim 20 wherein the void comprises a substantially circular cross-sectioned contact opening.

26. The semiconductor processing method of claim 20 wherein the void comprises an elongated trough.