Semiconductor device in a resin package housed in a frame having high thermal conductivity

• US 5,625,222 A
• Filed: 07/27/1994
• Issued: 04/29/1997
• Est. Priority Date: 11/18/1993
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Tsuji, Kazuto, Yoneda, Yoshiyuki
• Primary Examiner(s): BROWN, PETER T
• Application Number:
  US08/281,098
• Time in Patent Office: 1,007 Days
• Field of Search: 257/700, 257/706, 257/712, 257/778, 257/703, 257/713, 257/796, 257/787, 257/687, 257/678, 257/690
• US Class Current: 257/687
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48235 connecting the wire to a via metallisation of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/24 solid or gel at the normal operating temperature of the device H01L23/3135 takes precedence
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H05K 1/0201 : Thermal arrangements, e.g. for cooling, heating or preventing overheating
• CPC Class Codes: H05K 3/303 : Surface mounted components, e.g. affixing before soldering, aligning means, spacing means H05K3/32 takes precedence
• CPC Class Codes: H05K 3/3431 : Leadless components
• CPC Class Codes: Y10T 29/49144 : by metal fusion
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.

Abstract

A semiconductor device including a substrate, solder bumps provided on a lower major surface of the substrate, a semiconductor chip provided on an upper major surface of the substrate, a resin package body provided on the upper major surface of the substrate so as to bury the semiconductor chip therein, a thermally conductive frame member having a flange part supporting the substrate at a rim part of the substrate, wherein the thermal conductive frame member has a thermal conductivity substantially larger than that of the resin package body and extending along to and in an intimate contact with side walls of the resin package body.

Claims

1. A semiconductor device, comprising:

a substrate having upper and lower major surfaces;

solder bumps provided on said lower major surface of said substrate;

a semiconductor chip provided on said upper major surface of said substrate;

a resin package body provided on said upper major surface of said substrate so as to bury said semiconductor chip therein, said resin package body having an upper major surface and side walls surrounding said package body;

a thermally conductive frame member having a thermal conductivity substantially greater than that of said resin package body and extending along to and in an intimate contact with said side walls of said resin package body thereby leaving the upper major surface of said resin package body exposed to the air;

said thermally conductive frame having a flange part supporting said substrate thereon at a rim part of said substrate.

2. A semiconductor device as claimed in claim 1, wherein said thermally conductive frame member carries a heat radiating fin structure on an outer, exposed surface thereof.

3. A semiconductor device as claimed in claim 1, wherein said thermally conductive frame member carries one or more projecting ribs on an inner surface thereof that intimately contacts with said side walls of said resin package body, such that said one or more ribs project into said resin package body.

4. A semiconductor device as claimed in claim 1, wherein said thermally conductive frame member carries one or more grooves extending along an inner periphery thereof.

5. A semiconductor device as claimed in claim 1, wherein said thermally conductive frame member carries a projection on an inner surface thereof facing said side walls of said resin package body in correspondence to a corner of said frame member, such that said projection engages with a mating depression on a corresponding corner of said resin package body.

6. A semiconductor device as claimed in claim 1, wherein said thermally conductive frame member comprises a material selected from a group consisting of aluminum, an aluminum alloy, copper and a copper alloy, and carries an oxide film thereon.

7. An electronic apparatus, comprising:

a substrate having upper and lower major surfaces and surrounded by a peripheral edge, said substrate carrying a plurality of conductive bumps on said lower major surface of said substrate;

a semiconductor chip provided on said upper major surface of said substrate in electrical connection with solder bumps;

a resin package body provided on said upper major surface of said substrate such that said resin package body encapsulates said semiconductor chip therein, said resin package body having a peripheral wall surrounding said resin package body; and

a frame member having a thermal conductivity larger than a thermal conductivity of said resin package body, said frame member being provided on said resin package body to surround said peripheral edge in a continuous and intimate contact with said peripheral wall of said package body; and

a printed circuit board having an upper major surface and carrying an interconnection conductor pattern on said upper major surface,

said substrate being provided on said upper major surface of said printed circuit board such that said plurality of conductive bumps establish electrical connections with corresponding conductor patterns on said upper major surface of said printed circuit board and such that said frame member establishes an intimate mechanical contact with said upper major surface of said substrate.

8. A semiconductor device as claimed in claim 7, wherein said frame member carries an insulating coating for electrically insulating the frame member.