On-clip high frequency reliability and failure test structures

• US 5,625,288 A
• Filed: 01/16/1996
• Issued: 04/29/1997
• Est. Priority Date: 10/22/1993
• Status: Expired due to Term

• Current Assignee: Sandia Corporation (Martin Marietta Corporation)
• Original Assignee: Sandia Corporation (Martin Marietta Corporation)
• Inventors: Snyder, Eric S., Campbell, David V.
• Primary Examiner(s): Nguyen, Vinh P.
• Application Number:
  US08/590,690
• Time in Patent Office: 469 Days
• Field of Search: 324/703, 324/73.1, 324/158.1, 324/765, 324/760, 324/763, 437/8, 371/22.1, 371/22.6, 371/15.1, 371/22.5, 371/25.1, 371/16.1, 368/118, 368/120
• US Class Current: 324/750.06
• CPC Class Codes: G01R 31/2858 Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection
• CPC Class Codes: G01R 31/30 Marginal testing, e.g. by varying supply voltage testing computers during standby operation or idle time G06F11/22

Abstract

Self-stressing test structures for realistic high frequency reliability characterizations. An on-chip high frequency oscillator, controlled by DC signals from off-chip, provides a range of high frequency pulses to test structures. The test structures provide information with regard to a variety of reliability failure mechanisms, including hot-carriers, electromigration, and oxide breakdown. The system is normally integrated at the wafer level to predict the failure mechanisms of the production integrated circuits on the same wafer.

Claims

1. An on-chip reliability and failure testing system comprising:

oscillator means for producing pulses at frequencies above about 100 kHz;

external DC control means for the oscillator to control the frequency and duty cycle of the pulses and measure the output of a test structure means; and

test structure means driven by the pulses from the oscillator means, said test structure means comprising at least one discreet microelectronic element dedicated solely to the testing system each of which element being configured so as to uniquely express a failure mechanism as it would occur in other functional microelectronic circuits on the chip that are not connected to the elements of the test system located on the chip.

2. The system of claim 1 wherein the oscillator frequency is matched to the operating frequency of the chip.

3. The system of claim 1 further including on-chip heating means for the test structure means.

4. The system of claim 3 further including on-chip temperature sensing means for determining the temperature of the test structure means.

5. The system of claim 1 further including on-chip temperature sensing means for determining the temperature of the test structure means.

6. The system of claim 1 wherein the oscillator means is a voltage controlled oscillator.

7. The system of claim 1 wherein the oscillator means is a current controlled oscillator.

8. The system of claim 1 wherein the test structure means is adapted to test for hot carrier induced degradation.

9. The system of claim 8 wherein the test structure means comprises a device containing at least one MOS transistor.

10. The system of claim 8 wherein the test structure means comprises a device containing at least one bipolar transistor.

11. The system of claim 1 wherein the test structure means is adapted to test for electromigration.

12. The system of claim 11 wherein the test structure means comprises a metal line.

13. The system of claim 1 wherein the test structure means is adapted to test for oxide breakdown.

14. The system of claim 13 wherein the test structure means is a capacitor.

15. The system of claim 1 further comprising means to buffer and control the pulses to the test structure means.

16. The system of claim 1 wherein said external DC control means comprises means to terminate the application of pulses to the test structure means and means to measure the parameters of the test structure means in a state where they are not receiving pulses from the oscillator means.

17. An on-chip testing system comprising:

oscillator means for producing pulses at frequencies above about 100 kHz;

external DC control means for the oscillator to control the frequency of the pulses;

test structure means driven by the pulses from the oscillator means;

means to buffer and control the pulses to the test structure means;

heating means for the test structure means; and

temperature sensing means for determining the temperature of the test structure means and wherein said buffer means, temperature means and test structure means are connected to said external DC control means.

18. The system of claim 17 wherein the oscillator means is a voltage controlled oscillator.

19. The system of claim 17 wherein the oscillator means is a current controlled oscillator.

20. The system of claim 17 wherein said external DC control means comprises means to terminate the application of pulses to the test structure means and means to measure the parameters of the test structure means in a state where they are not receiving pulses from the oscillator means.

21. The system of claim 17 wherein the test structure means comprise at least two separate test structures stressed in parallel.

22. The system of claim 21 wherein the test structure means are selected from the group consisting of hot carrier test structures, electromigration test structures, oxide integrity test structures, and combinations thereof.