Low cost monolithic gallium arsenide upconverter chip

• US 5,625,307 A
• Filed: 03/03/1992
• Issued: 04/29/1997
• Est. Priority Date: 03/03/1992
• Status: Expired due to Term

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Anadigics Incorporated (Coherent Corp.)
• Inventors: Scheinberg, Norman R.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): PHAN, TRONG Q
• Application Number:
  US07/845,293
• Time in Patent Office: 1,883 Days
• Field of Search: 307/520, 307/529, 307/304, 365/194, 328/167, 328/156, 455/325, 455/326, 455/333, 333/4, 333/25, 333/119, 327/2, 327/39, 327/551, 327/552, 327/562, 327/563, 327/431, 327/436, 327/543, 327/168, 327/190, 327/304, 327/443, 327/579, 327/113, 327/122, 327/565
• US Class Current: 327/113
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03D 2200/0019 Gilbert multipliers
• CPC Class Codes: H03D 2200/0025 Gain control circuits
• CPC Class Codes: H03D 2200/0027 including arrangements for assuring the same gain in two paths
• CPC Class Codes: H03D 2200/0043 Bias and operating point
• CPC Class Codes: H03D 2200/0084 Lowering the supply voltage and saving power
• CPC Class Codes: H03D 7/125 with field effect transistors
• CPC Class Codes: H03D 7/14 Balanced arrangements
• CPC Class Codes: H03D 7/1408 with diodes
• CPC Class Codes: H03D 7/1441 using field-effect transistors H03D7/145 takes precedence
• CPC Class Codes: H03D 7/1458 Double balanced arrangements, i.e. where both input signals are differential
• CPC Class Codes: H03D 7/1483 comprising components for selecting a particular frequency component of the output
• CPC Class Codes: H03D 7/1491 Arrangements to linearise a transconductance stage of a mixer arrangement
• CPC Class Codes: H03D 7/18 Modifications of frequency-changers for eliminating image frequencies H03D7/16 takes precedence
• CPC Class Codes: H03D 9/0675 using field effect transistors H03D9/0683 takes precedence
• CPC Class Codes: H03F 2203/45228 A transformer being added at the output or the load circuit of the dif amp
• CPC Class Codes: H03F 2203/45256 One or more reactive elements are added in the source circuit of the amplifying FETs of the dif amp
• CPC Class Codes: H03F 2203/45258 Resistors are added in the source circuit of the amplifying FETs of the dif amp
• CPC Class Codes: H03F 2203/45458 the CSC comprising one or more capacitors
• CPC Class Codes: H03F 2203/45464 : the CSC comprising one or more coils
• CPC Class Codes: H03F 2203/45466 : the CSC being controlled, e.g. by a signal derived from a non specified place in the dif amp circuit
• CPC Class Codes: H03F 3/45197 : Pl types H03F3/45224, H03F3/45251 take precedence

Abstract

A monolithic upconverter integrated circuit is described which performs the first frequency conversion of a dual conversion cable television (CATV) receiver. The upconverter chip includes three functional blocks: a Gilbert type image-rejecting mixer, a phase splitter, and a voltage-controlled oscillator. Mixing is performed by a novel Gilbert type mixer including image-rejection inductors to improve the noise figure of the mixer. A differential circuit topology allows the monolithic upconverter chip to utilize a plastic dual inline batwing package without considerable performance loss. On-chip RF bypass networks, in the form of series RC terminations, also help compensate for the undesirable effects of pin inductances in the dual inline package. A resistor-based DC biasing scheme dramatically reduces power-up latency, allowing faster testing.

Claims

1. A low noise upconverter chip for modulating an RF input signal to a higher frequency IF output signal, said upconverter chip including a mixer circuit in combination with and packaged in a low cost plastic dual inline package having a plurality of pins.

2. An upconverter chip as defined in claim 1, wherein the mixer employs a balanced circuit topology to reduce the sensitivity of the upconverter chip performance to the parasitic inductances of the pins.

3. An upconverter chip as defined in claim 1, wherein the mixer is a Gilbert type image-rejecting mixer for mixing the RF input signal with a LO signal to generate the IF output signal wherein said mixer attenuates signals at the image frequency, thereby reducing noise in the IF output signal contributed by electronic devices producing broadband noise at said image frequency.

4. A low noise upconverter chip for modulating an RF input signal to a higher frequency IF output signal, said upconverter chip including a mixer circuit in combination with and packaged in a low cost plastic dual inline package having a plurality of pins, said upconverter chip including at least one on-chip passive RF bypass network wherein each passive RF bypass network is connected to a pin to dampen the spurious resonance caused by the parasitic inductance of the pin.

5. A low noise upconverter chip for modulating an RF input signal to a higher frequency IF output signal, said upconverter chip including a mixer circuit in combination with and packaged in a low cost plastic dual inline package having a plurality of pins, said upconverter chip further including at least one on-chip passive RF bypass network wherein each said passive RF bypass network is connected to a pin to dampen the spurious resonance caused by the parasitic inductance of the pin,

each said passive RF bypass network comprising a capacitor having first and second terminals, wherein the first terminal of the capacitor is connected to an AC ground node in the upconverter chip, and

a resistor connected between the second terminal of the capacitor and a pin of the package, with resistance chosen to dampen the spurious resonance caused by the parasitic inductance of the pin.

6. A low noise upconverter chip for modulating an rf input signal to a higher frequency IF output signal, said upconverter chip including a mixer circuit in combination with and packaged in a low cost plastic dual inline package having a plurality of pins, wherein the mixer is a Gilbert type image-rejecting mixer comprising:

a source degenerated first differential pair comprising matched first and second MESFETs, each having source, gate and drain terminals, and matched first and second inductors, wherein the source degenerating element for the first MESFET comprises the first matched inductor and the source degenerating element for the second MESFET comprises the second matched inductor, and the gates of the first and second MESFETs receive the RF input signal; and

a second differential pair comprising matched third and fourth MESFETs, each having source, gate and drain terminals, and a third differential pair comprising matched fifth and sixth MESFETs, each having source, gate and drain terminals, wherein the sources of the third and fourth MESFETs connect to the drain of the first MESFET and the sources of the fifth and sixth MESFETs connect to the drain of the second MESFET, the gate of the third MESFET connects to the gate of the fifth MESFET and the gate of the fourth MESFET connects to the gate of the sixth MESFET, the drain of the third MESFET connects to the drain of the sixth MESFET and the drain of the fourth MESFET connects to the drain of the fifth MESFET, the gates of the third and fourth MESFETs receive a differential LO signal and the drains of the third and fourth MESFETs supply the IF output signal.

7. The upconverter chip as defined in claim 6, further comprising:

a phase splitter for generating the differential LO signal from a single-ended LO signal.

8. The upconverter chip as defined in claim 7, further comprising:

a voltage-controlled local oscillator for generating the single-ended LO signal.

9. A low noise upconverter chip for modulating an RF input signal to a higher frequency IF output signal, said upconverter chip including a mixer circuit in combination with and packaged in a low cost plastic dual inline package having a plurality of pins, wherein the mixer is a Gilbert type image-rejecting mixer comprising:

a source degenerated first differential pair comprising matched first and second MESFETs, each having source, gate and drain terminals, and matched first and second inductors, wherein the source degenerating element for the first MESFET comprises the first matched inductor and the source degenerating element for the second MESFET comprises the second matched inductor, and the gates of the first and second MESFETs receive the RF input signal;

a second differential pair comprising matched third and fourth MESFETs, each having source, gate and drain terminals, and a third differential pair comprising matched fifth and sixth MESFETs, each having source, gate and drain terminals, wherein the sources of the third and fourth MESFETs connect to the drain of the first MESFET and the sources of the fifth and sixth MESFETs connect to the drain of the second MESFET, the gate of the third MESFET connects to the gate of the fifth MESFET and the gate of the fourth MESFET connects to the gate of the sixth MESFET, the drain of the third MESFET connects to the drain of the sixth MESFET and the drain of the fourth MESFET connects to the drain of the fifth MESFET, the gates of the third and fourth MESFETs receive a differential LO signal and the drains of the third and fourth MESFETs supply the IF output signal; and

first and second matched source-degenerating resistors, where the first resistor is connected in series with the first matched inductor, the serially connected first resistor and first matched inductor being connected between the source of the first MESFET and a virtual ground node, and the second resistor is connected in series with the second matched inductors, the serially connected second resistor and second matched inductor being connected between the source of the second MESFET and the virtual ground node.

10. A low noise upconverter chip for modulating an RF input signal to a higher frequency IF output signal, said upconverter chip including a mixer circuit in combination with and packaged in a low cost plastic dual inline package having a plurality of pins, wherein the mixer is a Gilbert type image-rejecting mixer comprising:

a source degenerated first differential pair comprising matched first and second MESFETs, each having source, gate and drain terminals, and matched first and second inductors, wherein the source degenerating element for the first MESFET comprises the first matched inductor and the source degenerating element for the second MESFET comprises the second matched inductor, and the gates of the first and second MESFETs receive the RF input signal;

a second differential pair comprising matched third and fourth MESFETs, each having source, gate and drain terminals, and a third differential pair comprising matched fifth and sixth MESFETs, each having source, gate and drain terminals, wherein the sources of the third and fourth MESFETs connect to the drain of the first MESFET and the sources of the fifth and sixth MESFETs connect to the drain of the second MESFET, the gate of the third MESFET connects to the gate of the fifth MESFET and the gate of the fourth MESFET connects to the gate of the sixth MESFET, the drain of the third MESFET connects to the drain of the sixth MESFET and the drain of the fourth MESFET connects to the drain of the fifth MESFET, the gates of the third and fourth MESFETs receive a differential LO signal and the drains of the third and fourth MESFETs supply the IF output signal; and

gain control means coupled between the matched first and second inductors for varying the gain between the RF signal and the IF signal.

11. An upconverter chip as defined in claim 10, wherein the gain control means comprises an AGC FET, said AGC FET being disposed between the first and second matched inductors and having source, drain and gate terminals, said source terminal being connected to one of the matched inductors and said drain terminal being connected to the other matched inductor so as to provide a variable resistance between said inductors.

12. An upconverter chip as defined in claim 11, wherein the gain control means further comprises:

a gain control terminal resistively coupled to the gate terminal of the AGC FET;

first capacitive means connected between the gate and drain terminals of the AGC FET; and

,

second capacitive means connected between the gate and source terminals of the AGC FET.

13. An upconverter as defined in claim 12, wherein the resistance between the gain control terminal and the gate terminal of the AGC FET is much larger than the RF signal frequency impedance of the first or second capacitive means.

14. An upconverter chip as defined in claim 12 wherein the capacitance of the first and second capacitive means is matched.

15. A low noise upconverter chip for modulating an RF input signal to a higher frequency IF output signal, said upconverter chip including a mixer circuit in combination with and packaged in a low cost plastic dual inline package having a plurality of pins, said upconverter chip further comprising a fast-settling DC bias circuit for biasing the mixer and reducing power-up latency in the upconverter chip.

16. A low noise upconverter chip for modulating an rf input signal to a higher frequency IF output signal, said upconverter chip including a mixer circuit in combination with and packaged in a low cost plastic dual inline package having of plurality of pins, said upconverter chip further comprising a fast-settling DC bias circuit for biasing the mixer and reducing power-up latency in the upconverter chip, said fast-settling DC bias circuit comprising:

a voltage dividing network including at least one internal node for generating a DC voltage at said internal node; and

a current source comprising a MESFET, having source, gate, and drain terminals, wherein the current flowing between source and drain terminals is responsive to the voltage on the MESFET gate terminal and the MESFET gate terminal is connected to said internal node in the voltage dividing network, and the drain terminal of the MESFET is connected to a virtual ground node of the mixer circuit.

17. The upconverter chip as defined in claim 16, wherein the voltage dividing network consists essentially of resistors.

18. The upconverter chip as defined in claim 16, wherein the current source further comprises a source degeneration resistor connected to the source terminal of the MESFET.

19. A Gilbert type image-rejecting mixer for mixing a differential RF signal with a differential LO signal to generate a differential IF signal, said mixer comprising:

a source degenerated first differential pair comprising matched first and second transistors, each having source, gate and drain terminals, and matched first and second inductors, wherein the source degenerating element for the first transistor comprises the first matched inductor and the source degenerating element for the second transistor comprises the second matched inductor, and the gates of the first and second transistors receive the differential RF input signal; and

a second differential pair comprising matched third and fourth transistors, each having source, gate and drain terminals, and a third differential pair comprising matched fifth and sixth transistors, each having source, gate and drain terminals, wherein the sources of the third and fourth transistors connect to the drain of the first transistor and the sources of the fifth and sixth transistors connect to the drain of the second transistor, the gate of the third transistor connects to the gate of the fifth transistor and the gate of the fourth transistor connects to the gate of the sixth transistor, the drain of the third transistor connects to the drain of the sixth transistor and the drain of the fourth transistor connects to the drain of the fifth transistor, the gates of the third and fourth transistors receive the differential LO signal and the drains of the third and fourth transistors supply the differential IF signal.

20. A Gilbert type image-rejecting mixer for mixing a different RF signal with a differential LO signal to generate a differential IF signal, said mixer comprising:

a source degenerated first differential pair comprising matched first and second transistors, each having source, gate and drain terminals, and matched first and second inductors, wherein the source degenerating element for the first transistor comprises the first matched inductor and the source degenerating element for the second transistor comprises the second matched inductor, and the gates of the first and second transistors receive the differential RF input signal;

a second differential pair comprising matched third and fourth transistors, each having source, gate and drain terminals, and a third differential pair comprising matched fifth and sixth transistors, each having source, gate and drain terminals, wherein the sources of the third and fourth transistors connect to the drain of the first transistor and the sources of the fifth and sixth transistors connect to the drain of the second transistor, the gate of the third transistor connects to the gate of the fifth transistor and the gate of the fourth transistor connects to the gate of the sixth transistor, the drain of the third transistor connects to the drain of the sixth transistor and the drain of the fourth transistors receive the differential LO signal and the drains of the third and fourth transistors supply the differential IF signal; and

gain control means coupled between the matched first and second inductors for varying the gain between the RF signal and the IF signal.

21. A mixer as defined in claim 20, wherein said gain control means comprises an AGC FET being disposed between the first and second matched inductors and having source, drain and gate terminals, said source terminal being connected to one of the matched inductors and said drain terminal being connected to the other matched inductor so as to provide a variable resistance between said inductors.

22. A Gilbert type image-rejecting mixer for mixing a different RF signal with a differential LO signal to generate a differential IF signal, said mixer comprising:

a source degenerated first differential pair comprising matched first and second transistors, each having source, gate and drain terminals, and matched first and second inductors, wherein the source degenerating element for the first transistor comprises the first matched inductor and the source degenerating element for the second transistor comprises the second matched inductor, and the gates of the first and second transistors receive the differential RF input signal;

a second differential pair comprising matched third and fourth transistors, each having source, gate and drain terminals, and a third differential pair comprising matched fifth and sixth transistors, each having source, gate and drain terminals, wherein the sources of the third and fourth transistors connect to the drain of the first transistor and the sources of the fifth and sixth transistors connect to the drain of the second transistor, the gate of the third transistor connects to the gate of the fifth transistor and the gate of the fourth transistor connects to the gate of the sixth transistor, the drain of the third transistor connects to the drain of the sixth transistor and the drain of the fourth transistors receive the differential LO signal and the drains of the third and fourth transistors supply the differential IF signal, wherein the transistors are GaAs MESFETs; and

first and second matched source-degenerating resistors, wherein the first resistor is connected in series with the first matched inductor, the serially connected first resistor and first matched inductor being connected between the source of the first MESFET and a virtual ground node, and the second resistor is connected in series with the second matched inductor, the serially connected second resistor and second matched inductor being connected between the source of the second MESFET and the virtual ground node.

23. A monolithic upconverter chip including a gilbert type image rejecting mixer, for mixing a differential RF signal with a differential LO signal to generate a differential IF signal, said mixer comprising:

a source degenerated first differential pair comprising matched first and second transistors, each having source, gate and drain terminals, and matched first and second inductors, wherein the source degenerating element for the first transistor comprises the first matched inductor and the source degenerating element for the second transistor comprises the second matched inductor, and the gates of the first and second transistors receive the differential RF input signal; and

a second differential pair comprising matched third and fourth transistors, each having source, gate and drain terminals, and a third differential pair comprising matched fifth and sixth transistors, each having source, gate and drain terminals, wherein the sources of the third and fourth transistors connect to the drain of the first transistor and the sources of the fifth and sixth transistors connect to the drain of the second transistor, the gate of the third transistor connects to the gate of the fifth transistor and the gate of the fourth transistor connects to the gate of the sixth transistor, the drain of the third transistor connects to the drain of the sixth transistor and the drain of the fourth transistor connects to the drain of the fifth transistor, the gates of the third and fourth transistors receive a differential LO signal and the drains of the third and fourth transistors supply the IF output signal.

24. A monolithic upconverter chip as defined in claim 23, further comprising a phase splitter for generating the differential LO signal from a single-ended LO signal.

25. A monolithic upconverter chip as defined in claim 24, further comprising a voltage-controlled local oscillator for generating the single-ended LO signal.